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/Linux-v5.10/drivers/clk/
Dclk-fixed-factor.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
13 * DOC: basic fixed multiplier and divider clock that cannot gate
15 * Traits of this clock:
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
19 * parent - fixed parent. No clk_set_parent support
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
29 do_div(rate, fix->div); in clk_factor_recalc_rate()
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Dam33xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for AM33xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
12 ti,bit-shift = <22>;
17 #clock-cells = <0>;
18 compatible = "fixed-factor-clock";
20 clock-mult = <1>;
21 clock-div = <1>;
25 #clock-cells = <0>;
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Domap36xx-omap3430es2plus-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP34xx/OMAP36xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,composite-no-wait-gate-clock";
12 ti,bit-shift = <0>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-divider-clock";
20 ti,bit-shift = <8>;
26 #clock-cells = <0>;
27 compatible = "ti,composite-clock";
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Dam43xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for AM43xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
12 ti,bit-shift = <31>;
17 #clock-cells = <0>;
18 compatible = "ti,mux-clock";
20 ti,bit-shift = <29>;
25 #clock-cells = <0>;
26 compatible = "ti,mux-clock";
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Dkeystone-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for Keystone 2 clock tree
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
9 #address-cells = <1>;
10 #size-cells = <1>;
14 #clock-cells = <0>;
15 compatible = "ti,keystone,pll-mux-clock";
18 bit-shift = <23>;
19 bit-mask = <1>;
20 clock-output-names = "mainmuxclk";
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Domap3xxx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP3 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
25 ti,bit-shift = <6>;
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Dmps2.dtsi6 * This file is dual-licensed: you can use it either under the terms
45 #include "armv7-m.dtsi"
48 #address-cells = <1>;
49 #size-cells = <1>;
51 oscclk0: clk-osc0 {
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <50000000>;
57 oscclk1: clk-osc1 {
58 compatible = "fixed-clock";
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Domap36xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP36xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,omap3-dpll-per-j-type-clock";
16 #clock-cells = <0>;
17 compatible = "ti,hsdiv-gate-clock";
19 ti,bit-shift = <0x1e>;
21 ti,set-rate-parent;
22 ti,set-bit-to-disable;
26 #clock-cells = <0>;
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Domap36xx-am35xx-omap3430es2plus-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <3>;
17 #clock-cells = <0>;
18 compatible = "fixed-factor-clock";
20 clock-mult = <1>;
21 clock-div = <5>;
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Ddra7xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for DRA7xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,dra7-atl-clock";
15 #clock-cells = <0>;
16 compatible = "ti,dra7-atl-clock";
21 #clock-cells = <0>;
22 compatible = "ti,dra7-atl-clock";
27 #clock-cells = <0>;
28 compatible = "ti,dra7-atl-clock";
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Domap54xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP5 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <12000000>;
15 #clock-cells = <0>;
16 compatible = "ti,gate-clock";
18 ti,bit-shift = <8>;
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
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/Linux-v5.10/drivers/clk/renesas/
Drcar-gen3-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
16 #include <linux/clk-provider.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-gen3-cpg.h"
32 #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
63 csn->saved = readl(csn->reg); in cpg_simple_notifier_call()
67 writel(csn->saved, csn->reg); in cpg_simple_notifier_call()
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Drcar-gen2-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen2 Clock Pulse Generator
10 #include <linux/clk-provider.h>
18 #include "renesas-cpg-mssr.h"
19 #include "rcar-gen2-cpg.h"
36 * Z Clock
38 * Traits of this clock:
39 * prepare - clk_prepare only ensures that parents are prepared
40 * enable - clk_enable only ensures that parents are enabled
41 * rate - rate is adjustable. clk->rate = parent->rate * mult / 32
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/Linux-v5.10/arch/arm64/boot/dts/broadcom/stingray/
Dstingray-clock.dtsi4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
33 #include <dt-bindings/clock/bcm-sr.h>
36 #clock-cells = <0>;
37 compatible = "fixed-clock";
38 clock-frequency = <50000000>;
42 #clock-cells = <0>;
43 compatible = "fixed-factor-clock";
45 clock-div = <2>;
46 clock-mult = <1>;
50 #clock-cells = <1>;
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/Linux-v5.10/drivers/clk/sunxi/
Dclk-a10-pll2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
10 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sun4i-a10-pll2.h>
22 #define SUN4I_PLL2_PRE_DIV_MASK GENMASK(SUN4I_PLL2_PRE_DIV_WIDTH - 1, 0)
26 #define SUN4I_PLL2_N_MASK GENMASK(SUN4I_PLL2_N_WIDTH - 1, 0)
30 #define SUN4I_PLL2_POST_DIV_MASK GENMASK(SUN4I_PLL2_POST_DIV_WIDTH - 1, 0)
41 const char *clk_name = node->name, *parent; in sun4i_pll2_setup()
44 struct clk_multiplier *mult; in sun4i_pll2_setup() local
62 prediv_clk = clk_register_divider(NULL, "pll2-prediv", in sun4i_pll2_setup()
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Dclk-sun4i-pll3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 #include <linux/clk-provider.h>
23 const char *clk_name = node->name, *parent; in sun4i_a10_pll3_setup()
24 struct clk_multiplier *mult; in sun4i_a10_pll3_setup() local
31 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_a10_pll3_setup()
36 pr_err("%s: Could not map the clock registers\n", clk_name); in sun4i_a10_pll3_setup()
44 gate->reg = reg; in sun4i_a10_pll3_setup()
45 gate->bit_idx = SUN4I_A10_PLL3_GATE_BIT; in sun4i_a10_pll3_setup()
46 gate->lock = &sun4i_a10_pll3_lock; in sun4i_a10_pll3_setup()
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/Linux-v5.10/drivers/clk/ti/
Dfixed-factor.c2 * TI Fixed Factor Clock
6 * Tero Kristo <t-kristo@ti.com>
18 #include <linux/clk-provider.h>
25 #include "clock.h"
31 * of_ti_fixed_factor_clk_setup - Setup function for TI fixed factor clock
32 * @node: device node for this clock
34 * Sets up a simple fixed factor clock based on device tree info.
39 const char *clk_name = node->name; in of_ti_fixed_factor_clk_setup()
41 u32 div, mult; in of_ti_fixed_factor_clk_setup() local
44 if (of_property_read_u32(node, "ti,clock-div", &div)) { in of_ti_fixed_factor_clk_setup()
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/Linux-v5.10/drivers/clk/mvebu/
Dorion.c1 // SPDX-License-Identifier: GPL-2.0
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include <linux/clk-provider.h>
60 int *mult, int *div) in mv88f5181_get_clk_ratio() argument
65 *mult = 1; in mv88f5181_get_clk_ratio()
68 *mult = 1; in mv88f5181_get_clk_ratio()
71 *mult = 0; in mv88f5181_get_clk_ratio()
89 CLK_OF_DECLARE(mv88f5181_clk, "marvell,mv88f5181-core-clock", mv88f5181_clk_init);
128 int *mult, int *div) in mv88f5182_get_clk_ratio() argument
133 *mult = 1; in mv88f5182_get_clk_ratio()
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/Linux-v5.10/arch/arm/mach-omap2/
Dclkt2xxx_dpllcore.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * DPLL + CORE_CLK composite clock functions
5 * Copyright (C) 2005-2008 Texas Instruments, Inc.
6 * Copyright (C) 2004-2010 Nokia Corporation
9 * Richard Woodruff <r-woodruff2@ti.com>
15 * XXX The DPLL and CORE clocks should be split into two separate clock
25 #include "clock.h"
29 #include "cm-regbits-24xx.h"
37 * (currently defined as "dpll_ck" in the OMAP2xxx clock tree). Set
43 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
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/Linux-v5.10/kernel/time/
Dtimekeeping.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/sched/clock.h>
26 #include "tick-internal.h"
61 * struct tk_fast - NMI safe timekeeper
74 /* Suspend-time cycles value for halted fast timekeeper. */
91 * returns nanoseconds already so no conversion is required, hence mult=1
97 .clock = &dummy_clock, \
99 .mult = 1, \
117 while (tk->tkr_mono.xtime_nsec >= ((u64)NSEC_PER_SEC << tk->tkr_mono.shift)) { in tk_normalize_xtime()
118 tk->tkr_mono.xtime_nsec -= (u64)NSEC_PER_SEC << tk->tkr_mono.shift; in tk_normalize_xtime()
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Dclockevents.c1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains functions which manage clock event devices.
5 * Copyright(C) 2005-2006, Thomas Gleixner <tglx@linutronix.de>
6 * Copyright(C) 2005-2007, Red Hat, Inc., Ingo Molnar
7 * Copyright(C) 2006-2007, Timesys Corp., Thomas Gleixner
17 #include "tick-internal.h"
19 /* The registered clock event devices */
35 u64 clc = (u64) latch << evt->shift; in cev_delta2ns()
38 if (WARN_ON(!evt->mult)) in cev_delta2ns()
39 evt->mult = 1; in cev_delta2ns()
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Dsched_clock.c1 // SPDX-License-Identifier: GPL-2.0
4 * counters to full 64-bit ns values.
13 #include <linux/sched/clock.h>
23 * struct clock_data - all data needed for sched_clock() (including
24 * registration of a new clock source)
29 * @wrap_kt: Duration for which clock can run before wrapping.
30 * @rate: Tick rate of the registered clock.
31 * @actual_read_sched_clock: Registered hardware level clock read function.
35 * into a single 64-byte cache line.
47 static int irqtime = -1;
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/Linux-v5.10/drivers/net/ethernet/mellanox/mlx4/
Den_clock.c14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
39 /* mlx4_en_read_clock - read raw cycle counter (to be used by time counter)
45 struct mlx4_dev *dev = mdev->dev; in mlx4_en_read_clock()
47 return mlx4_read_clock(dev) & tc->mask; in mlx4_en_read_clock()
55 lo = (u64)be16_to_cpu(ts_cqe->timestamp_lo); in mlx4_en_get_cqe_ts()
56 hi = ((u64)be32_to_cpu(ts_cqe->timestamp_hi) + !lo) << 16; in mlx4_en_get_cqe_ts()
69 seq = read_seqbegin(&mdev->clock_lock); in mlx4_en_fill_hwtstamps()
70 nsec = timecounter_cyc2time(&mdev->clock, timestamp); in mlx4_en_fill_hwtstamps()
71 } while (read_seqretry(&mdev->clock_lock, seq)); in mlx4_en_fill_hwtstamps()
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/Linux-v5.10/Documentation/devicetree/bindings/clock/
Dfixed-factor-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Binding for simple fixed factor rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
16 - allwinner,sun4i-a10-pll3-2x-clk
17 - fixed-factor-clock
19 "#clock-cells":
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/Linux-v5.10/Documentation/devicetree/bindings/clock/ti/
Dfixed-factor-clock.txt1 Binding for TI fixed factor rate clock sources.
3 Binding status: Unstable - ABI compatibility may be broken in the future
5 This binding uses the common clock binding[1], and also uses the autoidle
6 support from TI autoidle clock [2].
8 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
9 [2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
12 - compatible : shall be "ti,fixed-factor-clock".
13 - #clock-cells : from common clock binding; shall be set to 0.
14 - ti,clock-div: fixed divider.
15 - ti,clock-mult: fixed multiplier.
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