1 // SPDX-License-Identifier: GPL-2.0-or-later
7  * Maxime Ripard <maxime.ripard@free-electrons.com>
10 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sun4i-a10-pll2.h>
22 #define SUN4I_PLL2_PRE_DIV_MASK		GENMASK(SUN4I_PLL2_PRE_DIV_WIDTH - 1, 0)
26 #define SUN4I_PLL2_N_MASK		GENMASK(SUN4I_PLL2_N_WIDTH - 1, 0)
30 #define SUN4I_PLL2_POST_DIV_MASK	GENMASK(SUN4I_PLL2_POST_DIV_WIDTH - 1, 0)
41 	const char *clk_name = node->name, *parent;  in sun4i_pll2_setup()
44 	struct clk_multiplier *mult;  in sun4i_pll2_setup()  local
62 	prediv_clk = clk_register_divider(NULL, "pll2-prediv",  in sun4i_pll2_setup()
69 		pr_err("Couldn't register the prediv clock\n");  in sun4i_pll2_setup()
78 	gate->reg = reg;  in sun4i_pll2_setup()
79 	gate->bit_idx = SUN4I_PLL2_ENABLE;  in sun4i_pll2_setup()
80 	gate->lock = &sun4i_a10_pll2_lock;  in sun4i_pll2_setup()
83 	mult = kzalloc(sizeof(struct clk_multiplier), GFP_KERNEL);  in sun4i_pll2_setup()
84 	if (!mult)  in sun4i_pll2_setup()
87 	mult->reg = reg;  in sun4i_pll2_setup()
88 	mult->shift = SUN4I_PLL2_N_SHIFT;  in sun4i_pll2_setup()
89 	mult->width = 7;  in sun4i_pll2_setup()
90 	mult->flags = CLK_MULTIPLIER_ZERO_BYPASS |  in sun4i_pll2_setup()
92 	mult->lock = &sun4i_a10_pll2_lock;  in sun4i_pll2_setup()
95 	base_clk = clk_register_composite(NULL, "pll2-base",  in sun4i_pll2_setup()
98 					  &mult->hw, &clk_multiplier_ops,  in sun4i_pll2_setup()
99 					  &gate->hw, &clk_gate_ops,  in sun4i_pll2_setup()
102 		pr_err("Couldn't register the base multiplier clock\n");  in sun4i_pll2_setup()
109 	 * PLL2-1x  in sun4i_pll2_setup()
117 	val |= (SUN4I_PLL2_POST_DIV_VALUE - post_div_offset) << SUN4I_PLL2_POST_DIV_SHIFT;  in sun4i_pll2_setup()
120 	of_property_read_string_index(node, "clock-output-names",  in sun4i_pll2_setup()
130 	 * PLL2-2x  in sun4i_pll2_setup()
132 	 * This clock doesn't use the post divider, and really is just  in sun4i_pll2_setup()
133 	 * a fixed divider from the PLL2 base clock.  in sun4i_pll2_setup()
135 	of_property_read_string_index(node, "clock-output-names",  in sun4i_pll2_setup()
143 	/* PLL2-4x */  in sun4i_pll2_setup()
144 	of_property_read_string_index(node, "clock-output-names",  in sun4i_pll2_setup()
152 	/* PLL2-8x */  in sun4i_pll2_setup()
153 	of_property_read_string_index(node, "clock-output-names",  in sun4i_pll2_setup()
161 	clk_data->clks = clks;  in sun4i_pll2_setup()
162 	clk_data->clk_num = SUN4I_PLL2_OUTPUTS;  in sun4i_pll2_setup()
168 	kfree(mult);  in sun4i_pll2_setup()
186 CLK_OF_DECLARE(sun4i_a10_pll2, "allwinner,sun4i-a10-pll2-clk",
194 CLK_OF_DECLARE(sun5i_a13_pll2, "allwinner,sun5i-a13-pll2-clk",