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/Linux-v6.1/Documentation/devicetree/bindings/clock/st/
Dst,clkgen-pll.txt7 [2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
12 "st,clkgen-pll0"
13 "st,clkgen-pll0-a0"
14 "st,clkgen-pll0-c0"
15 "st,clkgen-pll1"
16 "st,clkgen-pll1-c0"
17 "st,stih407-clkgen-plla9"
18 "st,stih418-clkgen-plla9"
29 compatible = "st,clkgen-c32";
34 compatible = "st,stih407-clkgen-plla9";
Dst,clkgen.txt34 [3] Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
35 [4] Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
46 compatible = "st,clkgen-c32";
51 compatible = "st,clkgen-pll0";
Dst,clkgen-mux.txt13 "st,stih407-clkgen-a9-mux"
25 compatible = "st,stih407-clkgen-a9-mux";
Dst,flexgen.txt57 [1] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
/Linux-v6.1/arch/arm/boot/dts/
Dstih410-clock.dtsi34 compatible = "st,clkgen-c32";
39 compatible = "st,stih407-clkgen-plla9";
49 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
70 compatible = "st,clkgen-c32";
75 compatible = "st,clkgen-pll0-a0";
91 compatible = "st,clkgen-c32";
96 compatible = "st,clkgen-pll0-c0";
103 compatible = "st,clkgen-pll1-c0";
145 compatible = "st,clkgen-c32";
168 compatible = "st,clkgen-c32";
[all …]
Dstih418-clock.dtsi34 compatible = "st,clkgen-c32";
39 compatible = "st,stih418-clkgen-plla9";
49 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
70 compatible = "st,clkgen-c32";
75 compatible = "st,clkgen-pll0-a0";
91 compatible = "st,clkgen-c32";
96 compatible = "st,clkgen-pll0-c0";
103 compatible = "st,clkgen-pll1-c0";
145 compatible = "st,clkgen-c32";
168 compatible = "st,clkgen-c32";
[all …]
Dstih407-clock.dtsi31 compatible = "st,clkgen-c32";
36 compatible = "st,stih407-clkgen-plla9";
43 compatible = "st,stih407-clkgen-a9-mux";
65 compatible = "st,clkgen-c32";
70 compatible = "st,clkgen-pll0-a0";
86 compatible = "st,clkgen-c32";
91 compatible = "st,clkgen-pll0-c0";
98 compatible = "st,clkgen-pll1-c0";
140 compatible = "st,clkgen-c32";
163 compatible = "st,clkgen-c32";
[all …]
Dstih418-b2199.dts103 st,tx-retime-src = "clkgen";
Dstih418-b2264.dts109 st,tx-retime-src = "clkgen";
Dstihxxx-b2120.dtsi147 st,tx-retime-src = "clkgen";
/Linux-v6.1/arch/riscv/boot/dts/starfive/
Djh7100.dtsi136 clkgen: clock-controller@11800000 { label
137 compatible = "starfive,jh7100-clkgen";
153 clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
154 <&clkgen JH7100_CLK_I2C0_APB>;
166 clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
167 <&clkgen JH7100_CLK_I2C1_APB>;
181 clocks = <&clkgen JH7100_CLK_GPIO_APB>;
193 clocks = <&clkgen JH7100_CLK_UART2_CORE>,
194 <&clkgen JH7100_CLK_UART2_APB>;
206 clocks = <&clkgen JH7100_CLK_UART3_CORE>,
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dadi,axi-clkgen.yaml4 $id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
7 title: Binding for Analog Devices AXI clkgen pcore clock generator
22 - adi,axi-clkgen-2.00.a
23 - adi,zynqmp-axi-clkgen-2.00.a
50 compatible = "adi,axi-clkgen-2.00.a";
Dnvidia,tegra20-car.yaml15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
17 CLKGEN provides the registers to program the PLLs. It controls most of
20 CLKGEN input signals include the external clock for the reference frequency
23 Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
Dnvidia,tegra124-car.yaml15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
17 CLKGEN provides the registers to program the PLLs. It controls most of
20 CLKGEN input signals include the external clock for the reference frequency
23 Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
Dstarfive,jh7100-audclk.yaml52 clocks = <&clkgen JH7100_CLK_AUDIO_SRC>,
53 <&clkgen JH7100_CLK_AUDIO_12288>,
54 <&clkgen JH7100_CLK_DOM7AHB_BUS>;
Dstarfive,jh7100-clkgen.yaml4 $id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml#
15 const: starfive,jh7100-clkgen
51 compatible = "starfive,jh7100-clkgen";
/Linux-v6.1/drivers/clk/st/
DMakefile2 obj-y += clkgen-mux.o clkgen-pll.o clkgen-fsyn.o clk-flexgen.o
Dclkgen-mux.c3 * clkgen-mux.c: ST GEN-MUX Clock driver
16 #include "clkgen.h"
110 CLK_OF_DECLARE(clkgen_a9mux, "st,stih407-clkgen-a9-mux",
Dclkgen-pll.c18 #include "clkgen.h"
830 CLK_OF_DECLARE(c32_pll0, "st,clkgen-pll0", clkgen_c32_pll0_setup);
837 CLK_OF_DECLARE(c32_pll0_a0, "st,clkgen-pll0-a0", clkgen_c32_pll0_a0_setup);
844 CLK_OF_DECLARE(c32_pll0_c0, "st,clkgen-pll0-c0", clkgen_c32_pll0_c0_setup);
851 CLK_OF_DECLARE(c32_pll1, "st,clkgen-pll1", clkgen_c32_pll1_setup);
858 CLK_OF_DECLARE(c32_pll1_c0, "st,clkgen-pll1-c0", clkgen_c32_pll1_c0_setup);
865 CLK_OF_DECLARE(c32_plla9, "st,stih407-clkgen-plla9", clkgen_c32_plla9_setup);
872 CLK_OF_DECLARE(c28_plla9, "st,stih418-clkgen-plla9", clkgen_c28_plla9_setup);
/Linux-v6.1/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-sti.c52 *| | clk-125/txclk | clkgen |
53 *| | clkgen | |
56 *| | |clkgen/phyclk-in |
69 * clkgen| 1 | 1 | n/a |
85 * clkgen| | |
91 * clkgen| | |
177 /* On GiGa clk source can be either ext or from clkgen */ in stih4xx_fix_retime_src()
181 /* Switch to clkgen for these speeds */ in stih4xx_fix_retime_src()
/Linux-v6.1/drivers/clk/
Dclk-axi-clkgen.c3 * AXI clkgen driver
569 .compatible = "adi,zynqmp-axi-clkgen-2.00.a",
573 .compatible = "adi,axi-clkgen-2.00.a",
582 .name = "adi-axi-clkgen",
592 MODULE_DESCRIPTION("Driver for the Analog Devices' AXI clkgen pcore clock generator");
DKconfig290 tristate "AXI clkgen driver"
294 Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
DMakefile24 obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
/Linux-v6.1/Documentation/devicetree/bindings/net/
Dsti-dwmac.txt25 posssible values from "txclk", "clk_125" or "clkgen".
/Linux-v6.1/Documentation/devicetree/bindings/pinctrl/
Dstarfive,jh7100-pinctrl.yaml179 clocks = <&clkgen JH7100_CLK_GPIO_APB>;
180 resets = <&clkgen JH7100_RSTN_GPIO_APB>;

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