| /Linux-v6.1/drivers/gpu/drm/i915/display/ |
| D | intel_cdclk.c | 42 * DOC: CDCLK / RAWCLK
47 * are the core display clock (CDCLK) and RAWCLK.
49 * CDCLK clocks most of the display pipe logic, and thus its frequency
54 * On several platforms the CDCLK frequency can be changed dynamically
56 * Typically changes to the CDCLK frequency require all the display pipes
59 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
60 * DMC will not change the active CDCLK frequency however, so that part
76 u8 (*calc_voltage_level)(int cdclk);
82 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
89 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
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| D | intel_cdclk.h | 19 unsigned int cdclk, vco, ref, bypass; member
27 * Logical configuration of cdclk (used for all scaling,
34 * Actual configuration of cdclk, can be different from the
39 /* minimum acceptable cdclk to satisfy bandwidth requirements */
41 /* minimum acceptable cdclk for each pipe */
49 /* forced minimum cdclk for glk+ audio w/a */
80 …k_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
82 …k_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
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| D | hsw_ips.c | 199 * the increased cdclk requirement into account when in hsw_crtc_state_ips_capable()
200 * calculating the new cdclk. in hsw_crtc_state_ips_capable()
202 * Should measure whether using a lower cdclk w/o IPS in hsw_crtc_state_ips_capable()
205 crtc_state->pixel_rate > i915->display.cdclk.max_cdclk_freq * 95 / 100) in hsw_crtc_state_ips_capable()
243 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ in hsw_ips_compute_config()
244 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100) in hsw_ips_compute_config()
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| D | intel_display_core.h | 108 * dpll and cdclk state is protected by connection_mutex dpll.lock serializes
252 /* Display CDCLK functions */
253 const struct intel_cdclk_funcs *cdclk; member
300 /* The current hardware cdclk configuration */
303 /* cdclk, divider, and ratio table from bspec */
309 } cdclk; member
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| D | intel_audio.c | 527 unsigned int fec_coeff, cdclk, vdsc_bpp; in calc_hblank_early_prog() local
535 cdclk = i915->display.cdclk.hw.cdclk; in calc_hblank_early_prog()
542 "lanes = %u vdsc_bpp = %u cdclk = %u\n", in calc_hblank_early_prog()
543 h_active, link_clk, lanes, vdsc_bpp, cdclk); in calc_hblank_early_prog()
545 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk)) in calc_hblank_early_prog()
554 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), in calc_hblank_early_prog()
555 mul_u32_u32(link_clk, cdclk)); in calc_hblank_early_prog()
959 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts) in get_aud_ts_cdclk_m_n() argument
966 aud_ts->n = cdclk * aud_ts->m / 24000; in get_aud_ts_cdclk_m_n()
974 get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref, i915->display.cdclk.hw.cdclk, &aud_ts); in intel_audio_cdclk_change_post()
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| D | intel_atomic_plane.c | 268 * No need to check against the cdclk state if in intel_plane_calc_min_cdclk()
269 * the min cdclk for the plane doesn't increase. in intel_plane_calc_min_cdclk()
271 * Ie. we only ever increase the cdclk due to plane in intel_plane_calc_min_cdclk()
273 * display blinking due to constant cdclk changes. in intel_plane_calc_min_cdclk()
284 * No need to recalculate the cdclk state if in intel_plane_calc_min_cdclk()
285 * the min cdclk for the pipe doesn't increase. in intel_plane_calc_min_cdclk()
287 * Ie. we only ever increase the cdclk due to plane in intel_plane_calc_min_cdclk()
289 * display blinking due to constant cdclk changes. in intel_plane_calc_min_cdclk()
296 "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n", in intel_plane_calc_min_cdclk()
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| D | intel_bw.c | 934 * No need to check against the cdclk state if in intel_bw_calc_min_cdclk()
935 * the min cdclk doesn't increase. in intel_bw_calc_min_cdclk()
937 * Ie. we only ever increase the cdclk due to bandwidth in intel_bw_calc_min_cdclk()
939 * display blinking due to constant cdclk changes. in intel_bw_calc_min_cdclk()
949 * No need to recalculate the cdclk state if in intel_bw_calc_min_cdclk()
950 * the min cdclk doesn't increase. in intel_bw_calc_min_cdclk()
952 * Ie. we only ever increase the cdclk due to bandwidth in intel_bw_calc_min_cdclk()
954 * display blinking due to constant cdclk changes. in intel_bw_calc_min_cdclk()
960 "new bandwidth min cdclk (%d kHz) > old min cdclk (%d kHz)\n", in intel_bw_calc_min_cdclk()
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| D | intel_dp_aux.c | 84 * The clock divider is based off the cdclk or PCH rawclk, and would in ilk_get_aux_clock_divider()
85 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and in ilk_get_aux_clock_divider()
89 freq = dev_priv->display.cdclk.hw.cdclk; in ilk_get_aux_clock_divider()
116 * derive the clock from CDCLK automatically). We still implement the in skl_get_aux_clock_divider()
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| D | intel_modeset_setup.c | 36 to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_crtc_disable_noatomic()
419 to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_modeset_readout_hw_state()
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| D | intel_backlight.c | 1124 clock = KHz(dev_priv->display.cdclk.hw.cdclk); in i9xx_hz_to_pwm()
1142 clock = KHz(dev_priv->display.cdclk.hw.cdclk); in i965_hz_to_pwm()
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| D | i9xx_plane.c | 377 * of cdclk when the sprite plane is enabled on the in i9xx_plane_ratio()
379 * never allowed to exceed 80% of cdclk. Let's just go in i9xx_plane_ratio()
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| D | intel_display_power.c | 1140 drm_err(&dev_priv->drm, "CDCLK source is not LCPLL\n"); in hsw_assert_cdclk()
1313 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in hsw_restore_lcpll()
1640 /* 4. Enable CDCLK. */ in icl_display_core_init()
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| D | intel_dpll_mgr.c | 1371 /* DPLL0 is always enabled since it drives CDCLK */ in skl_ddi_dpll0_get_hw_state()
1869 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in skl_update_dpll_ref_clks()
3873 * DVFS pre sequence would be here, but in our driver the cdclk code in combo_pll_enable()
3893 * DVFS pre sequence would be here, but in our driver the cdclk code in tbt_pll_enable()
3916 * DVFS pre sequence would be here, but in our driver the cdclk code in mg_pll_enable()
3935 * DVFS pre sequence would be here, but in our driver the cdclk code in icl_pll_disable()
3993 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in icl_update_dpll_ref_clks()
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| D | intel_display.c | 2668 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10; in intel_crtc_compute_pipe_mode()
4772 cdclk_state->logical.cdclk); in hsw_ips_linetime_wm()
6266 * the planes' minimum cdclk calculation. Add such planes in intel_atomic_check_planes()
6267 * to the state before we compute the minimum cdclk. in intel_atomic_check_planes()
8379 cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_modeset_init_hw()
8382 intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK"); in intel_modeset_init_hw()
8383 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; in intel_modeset_init_hw()
8750 if (i915->display.cdclk.max_cdclk_freq == 0) in intel_modeset_init_nogem()
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| D | intel_tv.c | 1293 * oversample clock on gen3, cdclk on gen4). Once the pipe in intel_tv_compute_config()
1322 * num = cdclk * (tv_mode->oversample >> !tv_mode->progressive); in intel_tv_compute_config()
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| /Linux-v6.1/drivers/clk/samsung/ |
| D | clk-exynos-audss.c | 129 struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; in exynos_audss_clk_probe() local
189 cdclk = devm_clk_get(dev, "cdclk"); in exynos_audss_clk_probe()
191 if (!IS_ERR(cdclk)) in exynos_audss_clk_probe()
192 mout_i2s_p[1] = __clk_get_name(cdclk); in exynos_audss_clk_probe()
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| D | clk-s5pv210-audss.c | 70 struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio; in s5pv210_audss_clk_probe() local
105 cdclk = devm_clk_get(&pdev->dev, "iiscdclk0"); in s5pv210_audss_clk_probe()
119 if (!IS_ERR(cdclk)) in s5pv210_audss_clk_probe()
120 mout_i2s_p[1] = __clk_get_name(cdclk); in s5pv210_audss_clk_probe()
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| /Linux-v6.1/sound/hda/ |
| D | hdac_i915.c | 25 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
26 * BCLK = CDCLK * M / N
53 default: /* default CDCLK 450MHz */ in snd_hdac_i915_set_bclk()
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| /Linux-v6.1/Documentation/devicetree/bindings/clock/ |
| D | samsung,exynos-audss-clock.yaml | 52 - const: cdclk
79 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
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| /Linux-v6.1/include/dt-bindings/sound/ |
| D | samsung-i2s.h | 5 #define CLK_I2S_CDCLK 0 /* the CDCLK (CODECLKO) gate clock */
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| /Linux-v6.1/include/linux/platform_data/ |
| D | asoc-s3c24xx_simtec.h | 13 * @output_cdclk: Need to output CDCLK to the codec
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| /Linux-v6.1/Documentation/devicetree/bindings/sound/ |
| D | samsung-i2s.yaml | 102 description: Names of the CDCLK I2S output clocks.
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| /Linux-v6.1/arch/arm/boot/dts/ |
| D | s3c64xx-pinctrl.dtsi | 334 i2s0_cdclk: i2s0-cdclk-pins {
346 i2s1_cdclk: i2s1-cdclk-pins {
360 i2s2_cdclk: i2s2-cdclk-pins {
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| /Linux-v6.1/drivers/gpu/drm/i915/gt/ |
| D | intel_gt_pm_debugfs.c | 507 drm_printf(p, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk); in intel_gt_pm_frequency_dump()
508 drm_printf(p, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq); in intel_gt_pm_frequency_dump()
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| /Linux-v6.1/sound/soc/samsung/ |
| D | i2s.c | 1077 /* Gate CDCLK by default */ in samsung_i2s_dai_probe()
1267 const char * const i2s_clk_desc[] = { "cdclk", "rclk_src", "prescaler" }; in i2s_register_clock_provider()
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