Lines Matching full:cdclk
42 * DOC: CDCLK / RAWCLK
47 * are the core display clock (CDCLK) and RAWCLK.
49 * CDCLK clocks most of the display pipe logic, and thus its frequency
54 * On several platforms the CDCLK frequency can be changed dynamically
56 * Typically changes to the CDCLK frequency require all the display pipes
59 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
60 * DMC will not change the active CDCLK frequency however, so that part
76 u8 (*calc_voltage_level)(int cdclk);
82 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
89 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
95 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); in intel_cdclk_modeset_calc_cdclk()
99 int cdclk) in intel_cdclk_calc_voltage_level() argument
101 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
107 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
113 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
119 cdclk_config->cdclk = 266667; in fixed_266mhz_get_cdclk()
125 cdclk_config->cdclk = 333333; in fixed_333mhz_get_cdclk()
131 cdclk_config->cdclk = 400000; in fixed_400mhz_get_cdclk()
137 cdclk_config->cdclk = 450000; in fixed_450mhz_get_cdclk()
152 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
166 cdclk_config->cdclk = 200000; in i85x_get_cdclk()
169 cdclk_config->cdclk = 250000; in i85x_get_cdclk()
172 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
177 cdclk_config->cdclk = 266667; in i85x_get_cdclk()
191 cdclk_config->cdclk = 133333; in i915gm_get_cdclk()
197 cdclk_config->cdclk = 333333; in i915gm_get_cdclk()
201 cdclk_config->cdclk = 190000; in i915gm_get_cdclk()
215 cdclk_config->cdclk = 133333; in i945gm_get_cdclk()
221 cdclk_config->cdclk = 320000; in i945gm_get_cdclk()
225 cdclk_config->cdclk = 200000; in i945gm_get_cdclk()
338 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in g33_get_cdclk()
344 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", in g33_get_cdclk()
346 cdclk_config->cdclk = 190476; in g33_get_cdclk()
359 cdclk_config->cdclk = 266667; in pnv_get_cdclk()
362 cdclk_config->cdclk = 333333; in pnv_get_cdclk()
365 cdclk_config->cdclk = 444444; in pnv_get_cdclk()
368 cdclk_config->cdclk = 200000; in pnv_get_cdclk()
375 cdclk_config->cdclk = 133333; in pnv_get_cdclk()
378 cdclk_config->cdclk = 166667; in pnv_get_cdclk()
417 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in i965gm_get_cdclk()
423 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", in i965gm_get_cdclk()
425 cdclk_config->cdclk = 200000; in i965gm_get_cdclk()
445 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; in gm45_get_cdclk()
448 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; in gm45_get_cdclk()
452 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", in gm45_get_cdclk()
454 cdclk_config->cdclk = 222222; in gm45_get_cdclk()
466 cdclk_config->cdclk = 800000; in hsw_get_cdclk()
468 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
470 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
472 cdclk_config->cdclk = 337500; in hsw_get_cdclk()
474 cdclk_config->cdclk = 540000; in hsw_get_cdclk()
497 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) in vlv_calc_voltage_level() argument
500 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ in vlv_calc_voltage_level()
502 else if (cdclk >= 266667) in vlv_calc_voltage_level()
512 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; in vlv_calc_voltage_level()
525 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", in vlv_get_cdclk()
551 if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
583 int cdclk = cdclk_config->cdclk; in vlv_set_cdclk() local
587 switch (cdclk) { in vlv_set_cdclk()
595 MISSING_CASE(cdclk); in vlv_set_cdclk()
600 * off and a CDCLK frequency other than the minimum, like when in vlv_set_cdclk()
620 "timed out waiting for CDclk change\n"); in vlv_set_cdclk()
623 if (cdclk == 400000) { in vlv_set_cdclk()
627 cdclk) - 1; in vlv_set_cdclk()
629 /* adjust cdclk divider */ in vlv_set_cdclk()
639 "timed out waiting for CDclk change\n"); in vlv_set_cdclk()
650 if (cdclk == 400000) in vlv_set_cdclk()
672 int cdclk = cdclk_config->cdclk; in chv_set_cdclk() local
676 switch (cdclk) { in chv_set_cdclk()
683 MISSING_CASE(cdclk); in chv_set_cdclk()
688 * off and a CDCLK frequency other than the minimum, like when in chv_set_cdclk()
704 "timed out waiting for CDclk change\n"); in chv_set_cdclk()
728 static u8 bdw_calc_voltage_level(int cdclk) in bdw_calc_voltage_level() argument
730 switch (cdclk) { in bdw_calc_voltage_level()
750 cdclk_config->cdclk = 800000; in bdw_get_cdclk()
752 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
754 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
756 cdclk_config->cdclk = 540000; in bdw_get_cdclk()
758 cdclk_config->cdclk = 337500; in bdw_get_cdclk()
760 cdclk_config->cdclk = 675000; in bdw_get_cdclk()
764 * at least what the CDCLK frequency requires. in bdw_get_cdclk()
767 bdw_calc_voltage_level(cdclk_config->cdclk); in bdw_get_cdclk()
770 static u32 bdw_cdclk_freq_sel(int cdclk) in bdw_cdclk_freq_sel() argument
772 switch (cdclk) { in bdw_cdclk_freq_sel()
774 MISSING_CASE(cdclk); in bdw_cdclk_freq_sel()
791 int cdclk = cdclk_config->cdclk; in bdw_set_cdclk() local
800 "trying to change cdclk frequency with cdclk not enabled\n")) in bdw_set_cdclk()
806 "failed to inform pcode about cdclk change\n"); in bdw_set_cdclk()
822 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); in bdw_set_cdclk()
835 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); in bdw_set_cdclk()
863 static u8 skl_calc_voltage_level(int cdclk) in skl_calc_voltage_level() argument
865 if (cdclk > 540000) in skl_calc_voltage_level()
867 else if (cdclk > 450000) in skl_calc_voltage_level()
869 else if (cdclk > 337500) in skl_calc_voltage_level()
923 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; in skl_get_cdclk()
933 cdclk_config->cdclk = 432000; in skl_get_cdclk()
936 cdclk_config->cdclk = 308571; in skl_get_cdclk()
939 cdclk_config->cdclk = 540000; in skl_get_cdclk()
942 cdclk_config->cdclk = 617143; in skl_get_cdclk()
951 cdclk_config->cdclk = 450000; in skl_get_cdclk()
954 cdclk_config->cdclk = 337500; in skl_get_cdclk()
957 cdclk_config->cdclk = 540000; in skl_get_cdclk()
960 cdclk_config->cdclk = 675000; in skl_get_cdclk()
971 * at least what the CDCLK frequency requires. in skl_get_cdclk()
974 skl_calc_voltage_level(cdclk_config->cdclk); in skl_get_cdclk()
978 static int skl_cdclk_decimal(int cdclk) in skl_cdclk_decimal() argument
980 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); in skl_cdclk_decimal()
1029 dev_priv->display.cdclk.hw.vco = vco; in skl_dpll0_enable()
1043 dev_priv->display.cdclk.hw.vco = 0; in skl_dpll0_disable()
1047 int cdclk, int vco) in skl_cdclk_freq_sel() argument
1049 switch (cdclk) { in skl_cdclk_freq_sel()
1052 cdclk != dev_priv->display.cdclk.hw.bypass); in skl_cdclk_freq_sel()
1073 int cdclk = cdclk_config->cdclk; in skl_set_cdclk() local
1079 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are in skl_set_cdclk()
1084 * minimum 308MHz CDCLK. in skl_set_cdclk()
1095 "Failed to inform PCU about cdclk change (%d)\n", ret); in skl_set_cdclk()
1099 freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco); in skl_set_cdclk()
1101 if (dev_priv->display.cdclk.hw.vco != 0 && in skl_set_cdclk()
1102 dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1107 if (dev_priv->display.cdclk.hw.vco != vco) { in skl_set_cdclk()
1110 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); in skl_set_cdclk()
1119 if (dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1126 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); in skl_set_cdclk()
1154 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in skl_sanitize_cdclk()
1157 if (dev_priv->display.cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1158 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in skl_sanitize_cdclk()
1169 skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk); in skl_sanitize_cdclk()
1175 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in skl_sanitize_cdclk()
1177 /* force cdclk programming */ in skl_sanitize_cdclk()
1178 dev_priv->display.cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1180 dev_priv->display.cdclk.hw.vco = -1; in skl_sanitize_cdclk()
1189 if (dev_priv->display.cdclk.hw.cdclk != 0 && in skl_cdclk_init_hw()
1190 dev_priv->display.cdclk.hw.vco != 0) { in skl_cdclk_init_hw()
1197 dev_priv->display.cdclk.hw.vco); in skl_cdclk_init_hw()
1201 cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_init_hw()
1206 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); in skl_cdclk_init_hw()
1207 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); in skl_cdclk_init_hw()
1214 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_uninit_hw()
1216 cdclk_config.cdclk = cdclk_config.bypass; in skl_cdclk_uninit_hw()
1218 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); in skl_cdclk_uninit_hw()
1229 u32 cdclk; member
1237 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
1238 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
1239 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
1240 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
1241 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
1246 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
1247 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
1248 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
1253 { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
1254 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1255 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1256 { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
1257 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1258 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1260 { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
1261 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1262 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1263 { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
1264 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1265 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1267 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
1268 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1269 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1270 { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
1271 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1272 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1277 { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 },
1278 { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 },
1279 { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 },
1280 { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 },
1281 { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 },
1282 { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 },
1284 { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 },
1285 { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 },
1286 { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 },
1287 { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 },
1288 { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 },
1289 { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 },
1291 { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 },
1292 { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 },
1293 { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 },
1294 { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 },
1295 { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 },
1296 { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 },
1301 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1302 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1303 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1305 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1306 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1307 { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
1309 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1310 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1311 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1316 { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
1317 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1318 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1319 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1320 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1322 { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
1323 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1324 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1325 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1326 { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
1328 { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
1329 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1330 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1331 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1332 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1337 { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
1338 { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
1339 { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 },
1340 { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a },
1341 { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa },
1342 { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a },
1343 { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 },
1344 { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 },
1345 { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee },
1346 { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de },
1347 { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
1348 { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
1349 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
1355 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk()
1359 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk()
1360 table[i].cdclk >= min_cdclk) in bxt_calc_cdclk()
1361 return table[i].cdclk; in bxt_calc_cdclk()
1364 "Cannot satisfy minimum cdclk %d with refclk %u\n", in bxt_calc_cdclk()
1365 min_cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk()
1369 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) in bxt_calc_cdclk_pll_vco() argument
1371 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk_pll_vco()
1374 if (cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_calc_cdclk_pll_vco()
1378 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk_pll_vco()
1379 table[i].cdclk == cdclk) in bxt_calc_cdclk_pll_vco()
1380 return dev_priv->display.cdclk.hw.ref * table[i].ratio; in bxt_calc_cdclk_pll_vco()
1382 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", in bxt_calc_cdclk_pll_vco()
1383 cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk_pll_vco()
1387 static u8 bxt_calc_voltage_level(int cdclk) in bxt_calc_voltage_level() argument
1389 return DIV_ROUND_UP(cdclk, 25000); in bxt_calc_voltage_level()
1392 static u8 icl_calc_voltage_level(int cdclk) in icl_calc_voltage_level() argument
1394 if (cdclk > 556800) in icl_calc_voltage_level()
1396 else if (cdclk > 312000) in icl_calc_voltage_level()
1402 static u8 ehl_calc_voltage_level(int cdclk) in ehl_calc_voltage_level() argument
1404 if (cdclk > 326400) in ehl_calc_voltage_level()
1406 else if (cdclk > 312000) in ehl_calc_voltage_level()
1408 else if (cdclk > 180000) in ehl_calc_voltage_level()
1414 static u8 tgl_calc_voltage_level(int cdclk) in tgl_calc_voltage_level() argument
1416 if (cdclk > 556800) in tgl_calc_voltage_level()
1418 else if (cdclk > 326400) in tgl_calc_voltage_level()
1420 else if (cdclk > 312000) in tgl_calc_voltage_level()
1463 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but in bxt_de_pll_readout()
1499 cdclk_config->cdclk = cdclk_config->bypass; in bxt_get_cdclk()
1533 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * in bxt_get_cdclk()
1536 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); in bxt_get_cdclk()
1542 * at least what the CDCLK frequency requires. in bxt_get_cdclk()
1545 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk); in bxt_get_cdclk()
1557 dev_priv->display.cdclk.hw.vco = 0; in bxt_de_pll_disable()
1562 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in bxt_de_pll_enable()
1574 dev_priv->display.cdclk.hw.vco = vco; in bxt_de_pll_enable()
1584 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n"); in icl_cdclk_pll_disable()
1586 dev_priv->display.cdclk.hw.vco = 0; in icl_cdclk_pll_disable()
1591 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in icl_cdclk_pll_enable()
1602 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n"); in icl_cdclk_pll_enable()
1604 dev_priv->display.cdclk.hw.vco = vco; in icl_cdclk_pll_enable()
1609 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in adlp_cdclk_pll_crawl()
1628 dev_priv->display.cdclk.hw.vco = vco; in adlp_cdclk_pll_crawl()
1652 int cdclk, int vco) in bxt_cdclk_cd2x_div_sel() argument
1654 /* cdclk = vco / 2 / div{1,1.5,2,4} */ in bxt_cdclk_cd2x_div_sel()
1655 switch (DIV_ROUND_CLOSEST(vco, cdclk)) { in bxt_cdclk_cd2x_div_sel()
1658 cdclk != dev_priv->display.cdclk.hw.bypass); in bxt_cdclk_cd2x_div_sel()
1673 int cdclk) in cdclk_squash_waveform() argument
1675 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in cdclk_squash_waveform()
1678 if (cdclk == dev_priv->display.cdclk.hw.bypass) in cdclk_squash_waveform()
1682 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in cdclk_squash_waveform()
1683 table[i].cdclk == cdclk) in cdclk_squash_waveform()
1686 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", in cdclk_squash_waveform()
1687 cdclk, dev_priv->display.cdclk.hw.ref); in cdclk_squash_waveform()
1696 int cdclk = cdclk_config->cdclk; in bxt_set_cdclk() local
1719 "Failed to inform PCU about cdclk change (err %d, freq %d)\n", in bxt_set_cdclk()
1720 ret, cdclk); in bxt_set_cdclk()
1724 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0) { in bxt_set_cdclk()
1725 if (dev_priv->display.cdclk.hw.vco != vco) in bxt_set_cdclk()
1728 if (dev_priv->display.cdclk.hw.vco != 0 && in bxt_set_cdclk()
1729 dev_priv->display.cdclk.hw.vco != vco) in bxt_set_cdclk()
1732 if (dev_priv->display.cdclk.hw.vco != vco) in bxt_set_cdclk()
1735 if (dev_priv->display.cdclk.hw.vco != 0 && in bxt_set_cdclk()
1736 dev_priv->display.cdclk.hw.vco != vco) in bxt_set_cdclk()
1739 if (dev_priv->display.cdclk.hw.vco != vco) in bxt_set_cdclk()
1743 waveform = cdclk_squash_waveform(dev_priv, cdclk); in bxt_set_cdclk()
1748 clock = cdclk; in bxt_set_cdclk()
1762 skl_cdclk_decimal(cdclk); in bxt_set_cdclk()
1769 cdclk >= 500000) in bxt_set_cdclk()
1794 "PCode CDCLK freq set failed, (err %d, freq %d)\n", in bxt_set_cdclk()
1795 ret, cdclk); in bxt_set_cdclk()
1806 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
1812 int cdclk, clock, vco; in bxt_sanitize_cdclk() local
1815 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in bxt_sanitize_cdclk()
1817 if (dev_priv->display.cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
1818 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_sanitize_cdclk()
1835 /* Make sure this is a legal cdclk value for the platform */ in bxt_sanitize_cdclk()
1836 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); in bxt_sanitize_cdclk()
1837 if (cdclk != dev_priv->display.cdclk.hw.cdclk) in bxt_sanitize_cdclk()
1840 /* Make sure the VCO is correct for the cdclk */ in bxt_sanitize_cdclk()
1841 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_sanitize_cdclk()
1842 if (vco != dev_priv->display.cdclk.hw.vco) in bxt_sanitize_cdclk()
1845 expected = skl_cdclk_decimal(cdclk); in bxt_sanitize_cdclk()
1847 /* Figure out what CD2X divider we should be using for this cdclk */ in bxt_sanitize_cdclk()
1849 clock = dev_priv->display.cdclk.hw.vco / 2; in bxt_sanitize_cdclk()
1851 clock = dev_priv->display.cdclk.hw.cdclk; in bxt_sanitize_cdclk()
1854 dev_priv->display.cdclk.hw.vco); in bxt_sanitize_cdclk()
1861 dev_priv->display.cdclk.hw.cdclk >= 500000) in bxt_sanitize_cdclk()
1869 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in bxt_sanitize_cdclk()
1871 /* force cdclk programming */ in bxt_sanitize_cdclk()
1872 dev_priv->display.cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
1875 dev_priv->display.cdclk.hw.vco = -1; in bxt_sanitize_cdclk()
1884 if (dev_priv->display.cdclk.hw.cdclk != 0 && in bxt_cdclk_init_hw()
1885 dev_priv->display.cdclk.hw.vco != 0) in bxt_cdclk_init_hw()
1888 cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_init_hw()
1892 * - The initial CDCLK needs to be read from VBT. in bxt_cdclk_init_hw()
1895 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0); in bxt_cdclk_init_hw()
1896 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); in bxt_cdclk_init_hw()
1898 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); in bxt_cdclk_init_hw()
1905 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_uninit_hw()
1907 cdclk_config.cdclk = cdclk_config.bypass; in bxt_cdclk_uninit_hw()
1910 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); in bxt_cdclk_uninit_hw()
1916 * intel_cdclk_init_hw - Initialize CDCLK hardware
1919 * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and
1922 * take care of turning CDCLK off/on as needed.
1933 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
1936 * Uninitialize CDCLK. This is done only during the display core
1960 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); in intel_cdclk_can_crawl()
1961 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); in intel_cdclk_can_crawl()
1982 return a->cdclk != b->cdclk && in intel_cdclk_can_squash()
1989 * intel_cdclk_needs_modeset - Determine if changong between the CDCLK
1991 * @a: first CDCLK configuration
1992 * @b: second CDCLK configuration
1995 * True if changing between the two CDCLK configurations
2001 return a->cdclk != b->cdclk || in intel_cdclk_needs_modeset()
2007 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
2010 * @a: first CDCLK configuration
2011 * @b: second CDCLK configuration
2014 * True if changing between the two CDCLK configurations
2034 return a->cdclk != b->cdclk && in intel_cdclk_can_cd2x_update()
2041 * intel_cdclk_changed - Determine if two CDCLK configurations are different
2042 * @a: first CDCLK configuration
2043 * @b: second CDCLK configuration
2046 * True if the CDCLK configurations don't match, false if they do.
2060 context, cdclk_config->cdclk, cdclk_config->vco, in intel_cdclk_dump_config()
2066 * intel_set_cdclk - Push the CDCLK configuration to the hardware
2068 * @cdclk_config: new CDCLK configuration
2071 * Program the hardware based on the passed in CDCLK state,
2080 if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config)) in intel_set_cdclk()
2083 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk)) in intel_set_cdclk()
2086 intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to"); in intel_set_cdclk()
2097 * Lock aux/gmbus while we change cdclk in case those in intel_set_cdclk()
2098 * functions use cdclk. Not all platforms/ports do, in intel_set_cdclk()
2127 intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config), in intel_set_cdclk()
2128 "cdclk state doesn't match!\n")) { in intel_set_cdclk()
2129 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]"); in intel_set_cdclk()
2135 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
2139 * new CDCLK state, if necessary.
2156 old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) { in intel_set_cdclk_pre_plane_update()
2164 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2168 * new CDCLK state, if necessary.
2185 old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) { in intel_set_cdclk_post_plane_update()
2234 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ in intel_crtc_compute_min_cdclk()
2238 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, in intel_crtc_compute_min_cdclk()
2240 * there may be audio corruption or screen corruption." This cdclk in intel_crtc_compute_min_cdclk()
2264 * "For DP audio configuration, cdclk frequency shall be set to in intel_crtc_compute_min_cdclk()
2266 * DP Link Frequency(MHz) | Cdclk frequency(MHz) in intel_crtc_compute_min_cdclk()
2283 * On Geminilake once the CDCLK gets as low as 79200 in intel_crtc_compute_min_cdclk()
2297 * cannot be higher than the VDSC clock (cdclk) in intel_crtc_compute_min_cdclk()
2306 * however in some cases the lowest possible CDCLK in intel_crtc_compute_min_cdclk()
2318 dev_priv->display.cdclk.max_cdclk_freq)); in intel_crtc_compute_min_cdclk()
2371 if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) { in intel_compute_min_cdclk()
2373 "required cdclk (%d kHz) exceeds max (%d kHz)\n", in intel_compute_min_cdclk()
2374 min_cdclk, dev_priv->display.cdclk.max_cdclk_freq); in intel_compute_min_cdclk()
2434 int min_cdclk, cdclk; in vlv_modeset_calc_cdclk() local
2440 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); in vlv_modeset_calc_cdclk()
2442 cdclk_state->logical.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2444 vlv_calc_voltage_level(dev_priv, cdclk); in vlv_modeset_calc_cdclk()
2447 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in vlv_modeset_calc_cdclk()
2449 cdclk_state->actual.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2451 vlv_calc_voltage_level(dev_priv, cdclk); in vlv_modeset_calc_cdclk()
2461 int min_cdclk, cdclk; in bdw_modeset_calc_cdclk() local
2471 cdclk = bdw_calc_cdclk(min_cdclk); in bdw_modeset_calc_cdclk()
2473 cdclk_state->logical.cdclk = cdclk; in bdw_modeset_calc_cdclk()
2475 bdw_calc_voltage_level(cdclk); in bdw_modeset_calc_cdclk()
2478 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); in bdw_modeset_calc_cdclk()
2480 cdclk_state->actual.cdclk = cdclk; in bdw_modeset_calc_cdclk()
2482 bdw_calc_voltage_level(cdclk); in bdw_modeset_calc_cdclk()
2511 * clock for eDP. This will affect cdclk as well. in skl_dpll0_vco()
2529 int min_cdclk, cdclk, vco; in skl_modeset_calc_cdclk() local
2541 cdclk = skl_calc_cdclk(min_cdclk, vco); in skl_modeset_calc_cdclk()
2544 cdclk_state->logical.cdclk = cdclk; in skl_modeset_calc_cdclk()
2546 skl_calc_voltage_level(cdclk); in skl_modeset_calc_cdclk()
2549 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); in skl_modeset_calc_cdclk()
2552 cdclk_state->actual.cdclk = cdclk; in skl_modeset_calc_cdclk()
2554 skl_calc_voltage_level(cdclk); in skl_modeset_calc_cdclk()
2566 int min_cdclk, min_voltage_level, cdclk, vco; in bxt_modeset_calc_cdclk() local
2576 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk); in bxt_modeset_calc_cdclk()
2577 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2580 cdclk_state->logical.cdclk = cdclk; in bxt_modeset_calc_cdclk()
2583 intel_cdclk_calc_voltage_level(dev_priv, cdclk)); in bxt_modeset_calc_cdclk()
2586 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in bxt_modeset_calc_cdclk()
2587 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2590 cdclk_state->actual.cdclk = cdclk; in bxt_modeset_calc_cdclk()
2592 intel_cdclk_calc_voltage_level(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2605 * We can't change the cdclk frequency, but we still want to in fixed_modeset_calc_cdclk()
2607 * the actual cdclk frequency. in fixed_modeset_calc_cdclk()
2646 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj); in intel_atomic_get_cdclk_state()
2665 * planes are part of the state. We can now compute the minimum cdclk in intel_cdclk_atomic_check()
2696 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, in intel_cdclk_init()
2765 "Can change cdclk via squasher\n"); in intel_modeset_calc_cdclk()
2770 "Can change cdclk via crawl\n"); in intel_modeset_calc_cdclk()
2775 "Can change cdclk cd2x divider with pipe %c active\n", in intel_modeset_calc_cdclk()
2779 /* All pipes must be switched off while we change the cdclk. */ in intel_modeset_calc_cdclk()
2785 "Modeset required for cdclk change\n"); in intel_modeset_calc_cdclk()
2789 "New cdclk calculated to be logical %u kHz, actual %u kHz\n", in intel_modeset_calc_cdclk()
2790 new_cdclk_state->logical.cdclk, in intel_modeset_calc_cdclk()
2791 new_cdclk_state->actual.cdclk); in intel_modeset_calc_cdclk()
2802 int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq; in intel_compute_max_dotclk()
2818 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2821 * Determine the maximum CDCLK frequency the platform supports, and also
2822 * derive the maximum dot clock frequency the maximum CDCLK frequency
2828 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
2829 dev_priv->display.cdclk.max_cdclk_freq = 552000; in intel_update_max_cdclk()
2831 dev_priv->display.cdclk.max_cdclk_freq = 556800; in intel_update_max_cdclk()
2833 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
2834 dev_priv->display.cdclk.max_cdclk_freq = 648000; in intel_update_max_cdclk()
2836 dev_priv->display.cdclk.max_cdclk_freq = 652800; in intel_update_max_cdclk()
2838 dev_priv->display.cdclk.max_cdclk_freq = 316800; in intel_update_max_cdclk()
2840 dev_priv->display.cdclk.max_cdclk_freq = 624000; in intel_update_max_cdclk()
2849 * Use the lower (vco 8640) cdclk values as a in intel_update_max_cdclk()
2862 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()
2871 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
2873 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
2875 dev_priv->display.cdclk.max_cdclk_freq = 540000; in intel_update_max_cdclk()
2877 dev_priv->display.cdclk.max_cdclk_freq = 675000; in intel_update_max_cdclk()
2879 dev_priv->display.cdclk.max_cdclk_freq = 320000; in intel_update_max_cdclk()
2881 dev_priv->display.cdclk.max_cdclk_freq = 400000; in intel_update_max_cdclk()
2883 /* otherwise assume cdclk is fixed */ in intel_update_max_cdclk()
2884 dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk; in intel_update_max_cdclk()
2890 dev_priv->display.cdclk.max_cdclk_freq); in intel_update_max_cdclk()
2897 * intel_update_cdclk - Determine the current CDCLK frequency
2900 * Determine the current CDCLK frequency.
2904 intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw); in intel_update_cdclk()
2907 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): in intel_update_cdclk()
2909 * of cdclk that generates 4MHz reference clock freq which is used to in intel_update_cdclk()
2910 * generate GMBus clock. This will vary with the cdclk freq. in intel_update_cdclk()
2914 DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000)); in intel_update_cdclk()
3191 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
3197 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3198 dev_priv->display.cdclk.table = dg2_cdclk_table; in intel_init_cdclk_hooks()
3200 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3203 dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; in intel_init_cdclk_hooks()
3205 dev_priv->display.cdclk.table = adlp_cdclk_table; in intel_init_cdclk_hooks()
3207 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3208 dev_priv->display.cdclk.table = rkl_cdclk_table; in intel_init_cdclk_hooks()
3210 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3211 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3213 dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs; in intel_init_cdclk_hooks()
3214 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3216 dev_priv->display.funcs.cdclk = &icl_cdclk_funcs; in intel_init_cdclk_hooks()
3217 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3219 dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs; in intel_init_cdclk_hooks()
3221 dev_priv->display.cdclk.table = glk_cdclk_table; in intel_init_cdclk_hooks()
3223 dev_priv->display.cdclk.table = bxt_cdclk_table; in intel_init_cdclk_hooks()
3225 dev_priv->display.funcs.cdclk = &skl_cdclk_funcs; in intel_init_cdclk_hooks()
3227 dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs; in intel_init_cdclk_hooks()
3229 dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs; in intel_init_cdclk_hooks()
3231 dev_priv->display.funcs.cdclk = &chv_cdclk_funcs; in intel_init_cdclk_hooks()
3233 dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs; in intel_init_cdclk_hooks()
3235 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3237 dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs; in intel_init_cdclk_hooks()
3239 dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs; in intel_init_cdclk_hooks()
3241 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3243 dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs; in intel_init_cdclk_hooks()
3245 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3247 dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs; in intel_init_cdclk_hooks()
3249 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3251 dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs; in intel_init_cdclk_hooks()
3253 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3255 dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs; in intel_init_cdclk_hooks()
3257 dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs; in intel_init_cdclk_hooks()
3259 dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs; in intel_init_cdclk_hooks()
3261 dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs; in intel_init_cdclk_hooks()
3263 dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs; in intel_init_cdclk_hooks()
3265 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()
3268 if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk, in intel_init_cdclk_hooks()
3270 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()