| /Linux-v5.10/tools/include/asm/ |
| D | barrier.h | 4 #include "../../arch/x86/include/asm/barrier.h"
6 #include "../../arch/arm/include/asm/barrier.h"
8 #include "../../arch/arm64/include/asm/barrier.h"
10 #include "../../arch/powerpc/include/asm/barrier.h"
12 #include "../../arch/s390/include/asm/barrier.h"
14 #include "../../arch/sh/include/asm/barrier.h"
16 #include "../../arch/sparc/include/asm/barrier.h"
18 #include "../../arch/tile/include/asm/barrier.h"
20 #include "../../arch/alpha/include/asm/barrier.h"
22 #include "../../arch/mips/include/asm/barrier.h"
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| /Linux-v5.10/include/linux/ |
| D | spinlock_up.h | 9 #include <asm/barrier.h>
32 barrier(); in arch_spin_lock()
40 barrier(); in arch_spin_trylock()
47 barrier(); in arch_spin_unlock()
54 #define arch_read_lock(lock) do { barrier(); (void)(lock); } while (0)
55 #define arch_write_lock(lock) do { barrier(); (void)(lock); } while (0)
56 #define arch_read_trylock(lock) ({ barrier(); (void)(lock); 1; })
57 #define arch_write_trylock(lock) ({ barrier(); (void)(lock); 1; })
58 #define arch_read_unlock(lock) do { barrier(); (void)(lock); } while (0)
59 #define arch_write_unlock(lock) do { barrier(); (void)(lock); } while (0)
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| D | preempt.h | 172 barrier(); \
177 barrier(); \
188 barrier(); \
195 barrier(); \
209 barrier(); \
215 barrier(); \
225 barrier(); \
230 barrier(); \
242 #define preempt_disable() barrier()
243 #define sched_preempt_enable_no_resched() barrier()
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| D | compiler-intel.h | 16 #define barrier() __memory_barrier() macro
17 #define barrier_data(ptr) barrier()
24 /* This should act as an optimization barrier on var.
25 * Given that this compiler does not have inline assembly, a compiler barrier
28 #define OPTIMIZER_HIDE_VAR(var) barrier()
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| /Linux-v5.10/Documentation/ |
| D | memory-barriers.txt | 29 particular barrier, and
34 for any particular barrier, but if the architecture provides less than
37 Note also that it is possible that a barrier may be a no-op for an
38 architecture because the way that arch works renders an explicit barrier
53 - Varieties of memory barrier.
57 - SMP barrier pairing.
58 - Examples of memory barrier sequences.
64 - Compiler barrier.
74 (*) Inter-CPU acquiring barrier effects.
85 (*) Kernel I/O barrier effects.
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| /Linux-v5.10/arch/sparc/include/asm/ |
| D | barrier_64.h | 6 * #51. Essentially, if a memory barrier occurs soon after a mispredicted
10 * It used to be believed that the memory barrier had to be right in the
11 * delay slot, but a case has been traced recently wherein the memory barrier
23 * the memory barrier explicitly into a "branch always, predicted taken"
44 barrier(); \
52 barrier(); \
56 #define __smp_mb__before_atomic() barrier()
57 #define __smp_mb__after_atomic() barrier()
59 #include <asm-generic/barrier.h>
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| /Linux-v5.10/arch/mips/include/asm/ |
| D | sync.h | 11 * Two types of barrier are provided:
18 * restrictions imposed by the barrier.
31 * b) Multiple variants of ordering barrier are provided which allow the
34 * than a barrier are observed prior to stores that are younger than a
35 * barrier & don't care about the ordering of loads then the 'wmb'
36 * ordering barrier can be used. Limiting the barrier's effects to stores
49 * A full completion barrier; all memory accesses appearing prior to this sync
56 * For now we use a full completion barrier to implement all sync types, until
66 * barrier since 2010 & omit 'rmb' barriers because the CPUs don't perform
104 * don't implicitly provide a memory barrier. In general this is most MIPS
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| D | barrier.h | 86 # define __smp_mb() barrier()
87 # define __smp_rmb() barrier()
88 # define __smp_wmb() barrier()
92 * When LL/SC does imply order, it must also be a compiler barrier to avoid the
124 * a completion barrier immediately preceding the LL instruction. Therefore we
125 * can skip emitting a barrier from __smp_mb__before_atomic().
140 #include <asm-generic/barrier.h>
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| /Linux-v5.10/arch/csky/include/asm/ |
| D | barrier.h | 12 * sync: completion barrier, all sync.xx instructions
19 * bar.brwarw: ordering barrier for all load/store instructions before it
20 * bar.brwarws: ordering barrier for all load/store instructions before it
22 * bar.brar: ordering barrier for all load instructions before it
23 * bar.brars: ordering barrier for all load instructions before it
25 * bar.bwaw: ordering barrier for all store instructions before it
26 * bar.bwaws: ordering barrier for all store instructions before it
45 #include <asm-generic/barrier.h>
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| /Linux-v5.10/tools/virtio/ringtest/ |
| D | main.h | 90 /* Compiler barrier - similar to what Linux uses */
91 #define barrier() asm volatile("" ::: "memory") macro
97 #define cpu_relax() barrier()
110 barrier(); in busy_wait()
125 * adds a compiler barrier.
128 barrier(); \
134 barrier(); \
138 #define smp_wmb() barrier()
158 barrier(); \ in __read_once_size()
160 barrier(); \ in __read_once_size()
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| D | virtio_ring_0_9.c | 133 /* Barrier A (for pairing) */ in add_inbuf()
140 /* Barrier A (for pairing) */ in add_inbuf()
145 /* Barrier A (for pairing) */ in add_inbuf()
163 /* Barrier B (for pairing) */ in get_buf()
169 /* Barrier B (for pairing) */ in get_buf()
221 /* Barrier D (for pairing) */ in enable_call()
231 /* Barrier C (for pairing) */ in kick_available()
253 /* Barrier C (for pairing) */ in enable_kick()
280 /* Barrier A (for pairing) */ in use_buf()
289 /* Barrier A (for pairing) */ in use_buf()
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| D | ring.c | 130 * add an explicit full barrier to avoid this. in add_inbuf()
132 barrier(); in add_inbuf()
136 /* Barrier A (for pairing) */ in add_inbuf()
151 /* Barrier B (for pairing) */ in get_buf()
182 /* Barrier D (for pairing) */ in enable_call()
192 /* Barrier C (for pairing) */ in kick_available()
214 /* Barrier C (for pairing) */ in enable_kick()
234 /* Barrier A (for pairing) */ in use_buf()
247 /* Barrier B (for pairing) */ in use_buf()
259 /* Barrier D (for pairing) */ in call_used()
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| /Linux-v5.10/include/asm-generic/ |
| D | barrier.h | 3 * Generic barrier definitions.
31 #define mb() barrier()
79 #define smp_mb() barrier()
83 #define smp_rmb() barrier()
87 #define smp_wmb() barrier()
148 #define smp_store_mb(var, value) do { WRITE_ONCE(var, value); barrier(); } while (0)
152 #define smp_mb__before_atomic() barrier()
156 #define smp_mb__after_atomic() barrier()
163 barrier(); \
173 barrier(); \
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| /Linux-v5.10/arch/s390/include/asm/ |
| D | barrier.h | 26 #define rmb() barrier()
27 #define wmb() barrier()
37 barrier(); \
45 barrier(); \
49 #define __smp_mb__before_atomic() barrier()
50 #define __smp_mb__after_atomic() barrier()
76 #include <asm-generic/barrier.h>
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| /Linux-v5.10/arch/arc/include/asm/ |
| D | barrier.h | 15 * Explicit barrier provided by DMB instruction
19 * - DMB guarantees SMP as well as local barrier semantics
20 * (asm-generic/barrier.h ensures sane smp_*mb if not defined here, i.e.
21 * UP: barrier(), SMP: smp_*mb == *mb)
23 * in the general case. Plus it only provides full barrier.
42 #include <asm-generic/barrier.h>
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| /Linux-v5.10/arch/ia64/include/asm/ |
| D | barrier.h | 3 * Memory barrier definitions. This is based on information published
48 #define __smp_mb__before_atomic() barrier()
49 #define __smp_mb__after_atomic() barrier()
59 barrier(); \
67 barrier(); \
72 * The group barrier in front of the rsm & ssm are necessary to ensure
77 #include <asm-generic/barrier.h>
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| /Linux-v5.10/arch/mips/mm/ |
| D | tlb-r3k.c | 32 #define BARRIER \ macro
51 entry++; /* BARRIER */ in local_flush_tlb_from()
96 start += PAGE_SIZE; /* BARRIER */ in local_flush_tlb_range()
101 if (idx < 0) /* BARRIER */ in local_flush_tlb_range()
133 start += PAGE_SIZE; /* BARRIER */ in local_flush_tlb_kernel_range()
138 if (idx < 0) /* BARRIER */ in local_flush_tlb_kernel_range()
166 BARRIER; in local_flush_tlb_page()
171 if (idx < 0) /* BARRIER */ in local_flush_tlb_page()
205 BARRIER; in __update_tlb()
210 if (idx < 0) { /* BARRIER */ in __update_tlb()
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| /Linux-v5.10/tools/arch/sparc/include/asm/ |
| D | barrier_64.h | 8 * #51. Essentially, if a memory barrier occurs soon after a mispredicted
12 * It used to be believed that the memory barrier had to be right in the
13 * delay slot, but a case has been traced recently wherein the memory barrier
25 * the memory barrier explicitly into a "branch always, predicted taken"
45 barrier(); \
52 barrier(); \
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| /Linux-v5.10/Documentation/core-api/ |
| D | atomic_ops.rst | 44 proper implicit or explicit read memory barrier is needed before reading the
65 or explicit memory barrier is needed before the value set with the operation
75 implicit or explicit memory barrier is used after possible runtime
80 barrier.
92 appropriate compiler and/or memory barrier for each use case. Failure
124 Alternatively, you could place a barrier() call in the loop.
184 ``READ_ONCE()`` OR ``WRITE_ONCE()`` DO NOT IMPLY A BARRIER!
222 memory barrier semantics which satisfy the above requirements, that is
232 This means that like atomic_{inc,dec}_return(), the memory barrier
244 Again, these primitives provide explicit memory barrier semantics around
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| /Linux-v5.10/arch/x86/include/asm/ |
| D | barrier.h | 51 /* Prevent speculative execution past this barrier. */
54 #define dma_rmb() barrier()
55 #define dma_wmb() barrier()
63 #define __smp_wmb() barrier()
69 barrier(); \
77 barrier(); \
85 #include <asm-generic/barrier.h>
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| /Linux-v5.10/tools/virtio/asm/ |
| D | barrier.h | 4 #define barrier() asm volatile("" ::: "memory") macro
6 #define virt_rmb() barrier()
7 #define virt_wmb() barrier()
13 barrier(); \
20 #error Please fill in barrier macros
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| /Linux-v5.10/arch/powerpc/kernel/ |
| D | smp-tbsync.c | 53 barrier(); in smp_generic_take_timebase()
59 barrier(); in smp_generic_take_timebase()
70 barrier(); in smp_generic_take_timebase()
96 barrier(); in start_contest()
99 barrier(); in start_contest()
104 barrier(); in start_contest()
125 barrier(); in smp_generic_give_timebase()
166 barrier(); in smp_generic_give_timebase()
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| D | security.c | 55 * functions as a barrier), but on which the hypervisor (KVM/Qemu) has in setup_barrier_nospec()
56 * not been updated, we would like to enable the barrier. Dropping the in setup_barrier_nospec()
58 * we potentially enable the barrier on systems where the host firmware in setup_barrier_nospec()
191 seq_buf_printf(&s, ", ori31 speculation barrier enabled"); in cpu_show_spectre_v1()
248 * Store-forwarding barrier support.
257 pr_info("stf-barrier: disabled on command line."); in handle_no_stf_barrier()
268 /* Until firmware tells us, we have the barrier with auto */ in handle_ssbd()
320 pr_info("stf-barrier: fallback barrier available\n"); in setup_stf_barrier()
322 pr_info("stf-barrier: hwsync barrier available\n"); in setup_stf_barrier()
324 pr_info("stf-barrier: eieio barrier available\n"); in setup_stf_barrier()
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| /Linux-v5.10/arch/alpha/include/asm/ |
| D | irqflags.h | 35 barrier(); in arch_local_irq_disable()
41 barrier(); in arch_local_irq_save()
47 barrier(); in arch_local_irq_enable()
53 barrier(); in arch_local_irq_restore()
55 barrier(); in arch_local_irq_restore()
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| /Linux-v5.10/tools/build/feature/ |
| D | test-pthread-barrier.c | 7 pthread_barrier_t barrier; in main() local
9 pthread_barrier_init(&barrier, NULL, 1); in main()
10 pthread_barrier_wait(&barrier); in main()
11 return pthread_barrier_destroy(&barrier); in main()
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