Lines Matching full:barrier

11  * Two types of barrier are provided:
18  *      restrictions imposed by the barrier.
31  *   b) Multiple variants of ordering barrier are provided which allow the
34  *      than a barrier are observed prior to stores that are younger than a
35  *      barrier & don't care about the ordering of loads then the 'wmb'
36  *      ordering barrier can be used. Limiting the barrier's effects to stores
49  * A full completion barrier; all memory accesses appearing prior to this sync
56  * For now we use a full completion barrier to implement all sync types, until
66  * barrier since 2010 & omit 'rmb' barriers because the CPUs don't perform
104  * don't implicitly provide a memory barrier. In general this is most MIPS
123  *    In order to avoid this we need to place a memory barrier (ie. a SYNC
134  *    In order to avoid this we need a memory barrier (ie. a SYNC instruction)
154  * barrier to be ineffective, requiring the use of 2 in sequence to provide an
155  * effective barrier as noted by commit 6b07d38aaa52 ("MIPS: Octeon: Use
156  * optimized memory barrier primitives."). Here we specify that the affected