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/Linux-v5.15/Documentation/devicetree/bindings/phy/
Dti,phy-j721e-wiz.yaml51 assigned-clocks:
55 assigned-clock-parents:
59 assigned-clock-rates:
96 assigned-clocks:
99 assigned-clock-parents:
105 - assigned-clocks
106 - assigned-clock-parents
122 assigned-clocks:
125 assigned-clock-parents:
131 - assigned-clocks
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/sound/
Dnvidia,tegra210-ahub.yaml42 assigned-clocks:
45 assigned-clock-parents:
48 assigned-clock-rates:
93 - assigned-clocks
94 - assigned-clock-parents
110 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
111 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
147 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
148 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
149 assigned-clock-rates = <1536000>;
[all …]
Dnvidia,tegra-audio-graph-card.yaml35 assigned-clocks:
39 assigned-clock-parents:
43 assigned-clock-rates:
53 - assigned-clocks
54 - assigned-clock-parents
69 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
72 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
73 assigned-clock-rates = <368640000>, <49152000>, <12288000>;
91 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
92 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
[all …]
Dbrcm,cygnus-audio.txt13 - assigned-clocks: PLL and leaf clocks
14 - assigned-clock-parents: parent clocks of the assigned clocks
16 - assigned-clock-rates: List of clock frequencies of the
17 assigned clocks
36 assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>,
40 assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>;
41 assigned-clock-rates = <1769470191>,
Dnvidia,tegra186-dspk.yaml40 assigned-clocks:
43 assigned-clock-parents:
46 assigned-clock-rates:
80 - assigned-clocks
81 - assigned-clock-parents
95 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
96 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
97 assigned-clock-rates = <12288000>;
Dnvidia,tegra210-dmic.yaml41 assigned-clocks:
44 assigned-clock-parents:
47 assigned-clock-rates:
81 - assigned-clocks
82 - assigned-clock-parents
95 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
96 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
97 assigned-clock-rates = <3072000>;
Dmt2701-afe-pcm.txt47 - assigned-clocks: list of input clocks and dividers for the audio system.
49 - assigned-clocks-parents: parent of input clocks of assigned clocks.
50 - assigned-clock-rates: list of clock frequencies of assigned clocks.
138 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
142 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
144 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
Dnvidia,tegra210-i2s.yaml54 assigned-clocks:
58 assigned-clock-parents:
62 assigned-clock-rates:
97 - assigned-clocks
98 - assigned-clock-parents
111 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
112 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
113 assigned-clock-rates = <1536000>;
/Linux-v5.15/include/media/
Dv4l2-mem2mem.h147 * @m2m_ctx: m2m context assigned to the instance given by struct &v4l2_m2m_ctx
157 * @m2m_ctx: m2m context assigned to the instance given by struct &v4l2_m2m_ctx
181 * @m2m_ctx: m2m context assigned to the instance given by struct &v4l2_m2m_ctx
200 * @m2m_ctx: m2m context assigned to the instance given by struct &v4l2_m2m_ctx
230 * @m2m_ctx: m2m context assigned to the instance given by struct &v4l2_m2m_ctx
243 * @m2m_ctx: m2m context assigned to the instance given by struct &v4l2_m2m_ctx
260 * @m2m_ctx: m2m context assigned to the instance given by struct &v4l2_m2m_ctx
272 * @m2m_ctx: m2m context assigned to the instance given by struct &v4l2_m2m_ctx
288 * @m2m_ctx: m2m context assigned to the instance given by struct &v4l2_m2m_ctx
301 * @m2m_ctx: m2m context assigned to the instance given by struct &v4l2_m2m_ctx
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Dimx7ulp.dtsi154 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
155 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
156 assigned-clock-rates = <24000000>;
166 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
167 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
168 assigned-clock-rates = <48000000>;
175 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
176 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
261 assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
262 assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
[all …]
Dexynos4412-odroid-common.dtsi126 assigned-clocks = <&clock CLK_FOUT_EPLL>;
127 assigned-clock-rates = <45158401>;
131 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
137 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
140 assigned-clock-rates = <0>, <0>,
208 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
210 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
211 assigned-clock-rates = <0>, <176000000>;
216 assigned-clocks = <&clock CLK_MOUT_FIMC1>,
218 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
[all …]
Dimx7d-remarkable2.dts48 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
50 assigned-clock-parents = <&clks IMX7D_CKIL>;
51 assigned-clock-rates = <0>, <32768>;
61 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
62 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
69 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
70 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
107 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
108 assigned-clock-rates = <400000000>;
Dimx7d-zii-rpu2.dts189 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
190 assigned-clock-rates = <884736000>;
211 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
213 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
214 assigned-clock-rates = <0>, <100000000>;
294 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
296 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
297 assigned-clock-rates = <0>, <100000000>;
457 assigned-clocks = <&cs2000>;
458 assigned-clock-rates = <24000000>;
[all …]
Dimx7d-pico.dtsi105 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
107 assigned-clock-parents = <&clks IMX7D_CKIL>;
108 assigned-clock-rates = <0>, <32768>;
121 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
123 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
124 assigned-clock-rates = <0>, <100000000>;
278 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
280 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
281 assigned-clock-rates = <0>, <24576000>;
313 assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
[all …]
Dimx7d-sdb.dts222 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
224 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
225 assigned-clock-rates = <0>, <100000000>;
249 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
251 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
252 assigned-clock-rates = <0>, <100000000>;
393 assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
396 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
397 assigned-clock-rates = <0>, <884736000>, <12288000>;
429 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
[all …]
Dimx7s-warp.dts84 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
85 assigned-clock-rates = <884736000>;
268 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
270 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
271 assigned-clock-rates = <0>, <36864000>;
278 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
279 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
286 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
287 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
295 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
[all …]
/Linux-v5.15/drivers/clk/
Dclk-conf.c20 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents()
27 rc = of_parse_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents()
46 rc = of_parse_phandle_with_args(node, "assigned-clocks", in __set_clk_parents()
57 pr_warn("clk: couldn't get assigned clock %d for %pOF\n", in __set_clk_parents()
85 of_property_for_each_u32(node, "assigned-clock-rates", prop, cur, rate) { in __set_clk_rates()
87 rc = of_parse_phandle_with_args(node, "assigned-clocks", in __set_clk_rates()
120 * of_clk_set_defaults() - parse and set assigned clocks configuration
124 * This function parses 'assigned-{clocks/clock-parents/clock-rates}' properties
127 * listed in its 'assigned-clocks' or 'assigned-clock-parents' properties.
/Linux-v5.15/Documentation/devicetree/bindings/clock/
Dclock-bindings.txt135 ==Assigned clock parents and rates==
139 node through assigned-clocks, assigned-clock-parents and assigned-clock-rates
140 properties. The assigned-clock-parents property should contain a list of parent
142 assigned-clock-rates property should contain a list of frequencies in Hz. Both
143 these properties should correspond to the clocks listed in the assigned-clocks
156 assigned-clocks = <&clkcon 0>, <&pll 2>;
157 assigned-clock-parents = <&pll 2>;
158 assigned-clock-rates = <0>, <460800>;
162 the <&pll 2> clock is assigned a frequency value of 460800 Hz.
/Linux-v5.15/arch/mips/boot/dts/img/
Dpistachio.dtsi51 assigned-clocks = <&clk_periph PERIPH_CLK_I2C0_PRE_DIV>,
53 assigned-clock-rates = <100000000>, <33333334>;
69 assigned-clocks = <&clk_periph PERIPH_CLK_I2C1_PRE_DIV>,
71 assigned-clock-rates = <100000000>, <33333334>;
87 assigned-clocks = <&clk_periph PERIPH_CLK_I2C2_PRE_DIV>,
89 assigned-clock-rates = <100000000>, <33333334>;
105 assigned-clocks = <&clk_periph PERIPH_CLK_I2C3_PRE_DIV>,
107 assigned-clock-rates = <100000000>, <33333334>;
141 assigned-clocks = <&clk_core CLK_I2S_DIV>;
142 assigned-clock-rates = <12288000>;
[all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/amdzen1/
Dfloating-point.json5 "BriefDescription": "Total number multi-pipe uOps assigned to all pipes.",
6 …ions it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to all pipes.",
12 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 3.",
13 …rations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 3.",
19 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 2.",
20 …rations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 2.",
26 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 1.",
27 …rations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 1.",
33 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 0.",
34 …rations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 0.",
[all …]
/Linux-v5.15/arch/arm64/boot/dts/ti/
Dk3-j721e-common-proc-board.dts513 assigned-clocks = <&k3_clks 157 371>;
514 assigned-clock-parents = <&k3_clks 157 400>;
515 assigned-clock-rates = <24576000>; /* for 48KHz */
567 assigned-clocks = <&k3_clks 152 1>,
571 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
644 assigned-clocks = <&wiz0_pll1_refclk>;
645 assigned-clock-parents = <&cmn_refclk1>;
649 assigned-clocks = <&wiz0_refclk_dig>;
650 assigned-clock-parents = <&cmn_refclk1>;
654 assigned-clocks = <&wiz1_pll1_refclk>;
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/media/i2c/
Dovti,ov9282.yaml27 assigned-clocks: true
28 assigned-clock-parents: true
29 assigned-clock-rates: true
78 assigned-clocks = <&ov9282_clk>;
79 assigned-clock-parents = <&ov9282_clk_parent>;
80 assigned-clock-rates = <24000000>;
Dsony,imx334.yaml27 assigned-clocks: true
28 assigned-clock-parents: true
29 assigned-clock-rates: true
77 assigned-clocks = <&imx334_clk>;
78 assigned-clock-parents = <&imx334_clk_parent>;
79 assigned-clock-rates = <24000000>;
Dsony,imx335.yaml27 assigned-clocks: true
28 assigned-clock-parents: true
29 assigned-clock-rates: true
78 assigned-clocks = <&imx335_clk>;
79 assigned-clock-parents = <&imx335_clk_parent>;
80 assigned-clock-rates = <24000000>;
Dsony,imx412.yaml27 assigned-clocks: true
28 assigned-clock-parents: true
29 assigned-clock-rates: true
78 assigned-clocks = <&imx412_clk>;
79 assigned-clock-parents = <&imx412_clk_parent>;
80 assigned-clock-rates = <24000000>;

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