| /Linux-v5.15/tools/perf/Documentation/ |
| D | perf-c2c.txt | 32 for cachelines with highest contention - highest number of HITM accesses.
178 - cacheline percentage of all Remote/Local HITM accesses
184 - sum of all cachelines accesses
187 - sum of all load accesses
190 - sum of all store accesses
193 L1Hit - store accesses that hit L1
194 L1Miss - store accesses that missed L1
200 - count of LLC load accesses, includes LLC hits and LLC HITMs
203 - count of remote load accesses, includes remote hits and remote HITMs
206 - count of local and remote DRAM accesses
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| /Linux-v5.15/tools/memory-model/Documentation/ |
| D | ordering.txt | 15 2. Ordered memory accesses. These operations order themselves
16 against some or all of the CPU's prior accesses or some or all
17 of the CPU's subsequent accesses, depending on the subcategory
20 3. Unordered accesses, as the name indicates, have no ordering
48 a device driver, which must correctly order accesses to a physical
68 accesses against all subsequent accesses from the viewpoint of all CPUs.
89 CPU's accesses into three groups:
242 Ordered Memory Accesses
245 The Linux kernel provides a wide variety of ordered memory accesses:
264 of the CPU's prior memory accesses. Release operations often provide
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| D | access-marking.txt | 1 MARKING SHARED-MEMORY ACCESSES
5 normal accesses to shared memory, that is "normal" as in accesses that do
7 document these accesses, both with comments and with special assertions
17 1. Plain C-language accesses (unmarked), for example, "a = b;"
33 Neither plain C-language accesses nor data_race() (#1 and #2 above) place
40 C-language accesses. It is permissible to combine #2 and #3, for example,
45 C-language accesses, but marking all accesses involved in a given data
54 data_race() and even plain C-language accesses is preferable to
82 reads can enable better checking of the remaining accesses implementing
129 the other accesses to the relevant shared variables. But please note
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| D | explanation.txt | 32 24. PLAIN ACCESSES AND DATA RACES
86 factors such as DMA and mixed-size accesses.) But on multiprocessor
87 systems, with multiple CPUs making concurrent accesses to shared
140 This pattern of memory accesses, where one CPU stores values to two
151 accesses by the CPUs.
276 In short, if a memory model requires certain accesses to be ordered,
278 if those accesses would form a cycle, then the memory model predicts
305 Atomic read-modify-write accesses, such as atomic_inc() or xchg(),
312 logical computations, control-flow instructions, or accesses to
342 po-loc is a sub-relation of po. It links two memory accesses when the
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| D | glossary.txt | 83 each pair of memory accesses, the outcome where r0, r1, and r2
118 its CPU's prior accesses with all of that CPU's subsequent
119 accesses, or a marked access such as atomic_add_return()
120 that orders all of its CPU's prior accesses, itself, and
121 all of its CPU's subsequent accesses.
123 Happens-Before (hb): A relation between two accesses in which LKMM
134 data between two CPUs requires that both CPUs their accesses.
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| /Linux-v5.15/include/linux/ |
| D | kcsan-checks.h | 4 * uninstrumented accesses, or change KCSAN checking behaviour of accesses.
57 * Accesses within the atomic region may appear to race with other accesses but
70 * Accesses within the atomic region may appear to race with other accesses but
81 * kcsan_atomic_next - consider following accesses as atomic
83 * Force treating the next n memory accesses for the current context as atomic
86 * @n: number of following memory accesses to treat as atomic.
93 * Set the access mask for all accesses for the current context if non-zero.
122 * Scoped accesses are implemented by appending @sa to an internal list for the
178 * Only use these to disable KCSAN for accesses in the current compilation unit;
243 * Check for atomic accesses: if atomic accesses are not ignored, this simply
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| D | virtio_pci_modern.h | 21 /* So we can sanity-check accesses. */
37 * Type-safe wrappers for io accesses.
41 * method, i.e. 32-bit accesses for 32-bit fields, 16-bit accesses
42 * for 16-bit fields and 8-bit accesses for 8-bit fields.
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| D | damon.h | 70 * @check_accesses: Check the accesses to target regions.
71 * @reset_aggregated: Reset aggregated accesses monitoring results.
91 * @check_accesses should check the accesses to each region that made after the
92 * last preparation and update the number of observed accesses of each region.
93 * It should also return max number of observed accesses that made as a result
129 * the accesses to the results.
152 * not. It aggregates and keeps the access information (number of accesses to
177 * @kdamond_lock. Accesses to other fields must be protected by themselves.
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| /Linux-v5.15/Documentation/core-api/ |
| D | unaligned-memory-access.rst | 2 Unaligned Memory Accesses
15 unaligned accesses, why you need to write code that doesn't cause them,
22 Unaligned memory accesses occur when you try to read N bytes of data starting
59 - Some architectures are able to perform unaligned memory accesses
61 - Some architectures raise processor exceptions when unaligned accesses
64 - Some architectures raise processor exceptions when unaligned accesses
72 memory accesses to happen, your code will not work correctly on certain
103 to pad structures so that accesses to fields are suitably aligned (assuming
136 lead to unaligned accesses when accessing fields that do not satisfy
183 Here is another example of some code that could cause unaligned accesses::
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| /Linux-v5.15/Documentation/dev-tools/ |
| D | kcsan.rst | 78 the racing thread, but could also occur due to e.g. DMA accesses. Such reports
85 It may be desirable to disable data race detection for specific accesses,
90 any data races due to accesses in ``expr`` should be ignored and resulting
92 `"Marking Shared-Memory Accesses" in the LKMM`_ for more information.
114 .. _"Marking Shared-Memory Accesses" in the LKMM: https://git.kernel.org/pub/scm/linux/kernel/git/t…
128 accesses are aligned writes up to word size.
190 In an execution, two memory accesses form a *data race* if they *conflict*,
194 Accesses and Data Races" in the LKMM`_.
196 .. _"Plain Accesses and Data Races" in the LKMM: https://git.kernel.org/pub/scm/linux/kernel/git/to…
236 KCSAN relies on observing that two accesses happen concurrently. Crucially, we
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| /Linux-v5.15/kernel/kcsan/ |
| D | permissive.h | 3 * Special rules for ignoring entire classes of data-racy memory accesses. None
44 * Rules here are only for plain read accesses, so that we still report in kcsan_ignore_data_race()
45 * data races between plain read-write accesses. in kcsan_ignore_data_race()
60 * While it is still recommended that such accesses be marked in kcsan_ignore_data_race()
66 * optimizations (including those that tear accesses), because no more in kcsan_ignore_data_race()
67 * than 1 bit changed, the plain accesses are safe despite the presence in kcsan_ignore_data_race()
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| /Linux-v5.15/arch/arm/include/uapi/asm/ |
| D | byteorder.h | 6 * that byte accesses appear as:
8 * and word accesses (data or instruction) appear as:
11 * When in big endian mode, byte accesses appear as:
13 * and word accesses (data or instruction) appear as:
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| D | swab.h | 6 * that byte accesses appear as:
8 * and word accesses (data or instruction) appear as:
11 * When in big endian mode, byte accesses appear as:
13 * and word accesses (data or instruction) appear as:
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| /Linux-v5.15/Documentation/i2c/ |
| D | i2c-topology.rst | 152 This means that accesses to D2 are lockout out for the full duration
153 of the entire operation. But accesses to D3 are possibly interleaved
216 This means that accesses to both D2 and D3 are locked out for the full
261 When device D1 is accessed, accesses to D2 are locked out for the
263 are locked). But accesses to D3 and D4 are possibly interleaved at
264 any point. Accesses to D3 locks out D1 and D2, but accesses to D4
282 When device D1 is accessed, accesses to D2 and D3 are locked out
284 root adapter). But accesses to D4 are possibly interleaved at any
295 mux. In that case, any interleaved accesses to D4 might close M2
316 When D1 is accessed, accesses to D2 are locked out for the full
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| /Linux-v5.15/tools/perf/pmu-events/arch/nds32/n13/ |
| D | atcpmu.json | 75 "PublicDescription": "uITLB accesses",
78 "BriefDescription": "V3 uITLB accesses"
81 "PublicDescription": "uDTLB accesses",
84 "BriefDescription": "V3 uDTLB accesses"
87 "PublicDescription": "MTLB accesses",
90 "BriefDescription": "V3 MTLB accesses"
108 "BriefDescription": "V3 ILM accesses"
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/amdzen1/ |
| D | recommended.json | 12 "BriefDescription": "All L1 Data Cache Accesses",
17 "BriefDescription": "All L2 Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35 "BriefDescription": "L2 Cache Accesses from L2 HWPF",
90 "BriefDescription": "L3 Accesses",
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/amdzen2/ |
| D | recommended.json | 12 "BriefDescription": "All L1 Data Cache Accesses",
17 "BriefDescription": "All L2 Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35 "BriefDescription": "L2 Cache Accesses from L2 HWPF",
90 "BriefDescription": "L3 Accesses",
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| /Linux-v5.15/arch/arm/include/asm/ |
| D | swab.h | 6 * that byte accesses appear as:
8 * and word accesses (data or instruction) appear as:
11 * When in big endian mode, byte accesses appear as:
13 * and word accesses (data or instruction) appear as:
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| /Linux-v5.15/Documentation/driver-api/ |
| D | device-io.rst | 10 Bus-Independent Device Accesses
30 part of the CPU's address space is interpreted not as accesses to
31 memory, but as accesses to a device. Some architectures define devices
54 historical accident, these are named byte, word, long and quad accesses.
55 Both read and write accesses are supported; there is no prefetch support
119 Port Space Accesses
127 addresses is generally not as fast as accesses to the memory mapped
136 Accesses to this space are provided through a set of functions which
137 allow 8-bit, 16-bit and 32-bit accesses; also known as byte, word and
143 that accesses to their ports are slowed down. This functionality is
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/amdzen3/ |
| D | recommended.json | 12 "BriefDescription": "All L1 Data Cache Accesses",
17 "BriefDescription": "All L2 Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35 "BriefDescription": "L2 Cache Accesses from L2 HWPF",
90 "BriefDescription": "L3 Cache Accesses",
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| /Linux-v5.15/lib/ |
| D | Kconfig.ubsan | 53 array accesses, where the array size is known at compile time.
82 Enabling this option detects errors due to accesses through a
116 bool "Perform checking for accesses beyond the end of objects"
123 This option enables -fsanitize=object-size which checks for accesses
150 This option enables the check of unaligned memory accesses.
152 accesses may produce a lot of false positives.
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/elkhartlake/ |
| D | frontend.json | 74 "EventName": "ICACHE.ACCESSES",
77 … accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count …
89 … accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count…
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| /Linux-v5.15/arch/mips/kvm/ |
| D | Kconfig | 34 bool "Maintain counters for COP0 accesses"
37 Maintain statistics for Guest COP0 accesses.
38 A histogram of COP0 accesses is printed when the VM is
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| /Linux-v5.15/Documentation/admin-guide/hw-vuln/ |
| D | special-register-buffer-data-sampling.rst | 8 infer values returned from special register accesses. Special register
9 accesses are accesses to off core registers. According to Intel's evaluation,
70 accesses from other logical processors will be delayed until the special
82 #. Executing RDRAND, RDSEED or EGETKEY will delay memory accesses from other
84 legacy locked cache-line-split accesses.
91 processors memory accesses. The opt-out mechanism does not affect Intel SGX
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| /Linux-v5.15/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/ |
| D | uncore-l3c.json | 5 "BriefDescription": "Total read accesses",
6 "PublicDescription": "Total read accesses",
12 "BriefDescription": "Total write accesses",
13 "PublicDescription": "Total write accesses",
|
