Lines Matching full:accesses

10 Bus-Independent Device Accesses
30 part of the CPU's address space is interpreted not as accesses to
31 memory, but as accesses to a device. Some architectures define devices
54 historical accident, these are named byte, word, long and quad accesses.
55 Both read and write accesses are supported; there is no prefetch support
119 Port Space Accesses
127 addresses is generally not as fast as accesses to the memory mapped
136 Accesses to this space are provided through a set of functions which
137 allow 8-bit, 16-bit and 32-bit accesses; also known as byte, word and
143 that accesses to their ports are slowed down. This functionality is
172   MMIO accesses and DMA accesses as well as fixed endianness for accessing
223   on 32-bit architectures but allow two consecutive 32-bit accesses instead.
236   architecture specific behavior. Accesses are usually atomic in the sense that
238   multiple consecutive accesses can be combined on the bus. In portable code, it
241   accesses or even spinlocks. The byte order is generally the same as for normal
310 * No reordering - The CPU may not reorder accesses to this memory mapping with
327 On many platforms, I/O accesses must be aligned with respect to the access
345 devices (e.g. buffers or shared memory), but care must be taken as accesses are
347 accesses without explicit barriers.