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/Linux-v5.15/drivers/usb/host/
Dxhci-tegra.c3 * NVIDIA Tegra xHCI host controller driver
20 #include <linux/phy/tegra/xusb.h>
32 #include <soc/tegra/pmc.h>
281 static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset) in fpci_readl() argument
283 return readl(tegra->fpci_base + offset); in fpci_readl()
286 static inline void fpci_writel(struct tegra_xusb *tegra, u32 value, in fpci_writel() argument
289 writel(value, tegra->fpci_base + offset); in fpci_writel()
292 static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset) in ipfs_readl() argument
294 return readl(tegra->ipfs_base + offset); in ipfs_readl()
297 static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value, in ipfs_writel() argument
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/Linux-v5.15/drivers/devfreq/
Dtegra30-devfreq.c3 * A devfreq driver for NVIDIA Tegra SoCs
22 #include <soc/tegra/fuse.h>
219 static u32 actmon_readl(struct tegra_devfreq *tegra, u32 offset) in actmon_readl() argument
221 return readl_relaxed(tegra->regs + offset); in actmon_readl()
224 static void actmon_writel(struct tegra_devfreq *tegra, u32 val, u32 offset) in actmon_writel() argument
226 writel_relaxed(val, tegra->regs + offset); in actmon_writel()
252 static void tegra_devfreq_update_avg_wmark(struct tegra_devfreq *tegra, in tegra_devfreq_update_avg_wmark() argument
255 u32 avg_band_freq = tegra->max_freq * ACTMON_DEFAULT_AVG_BAND / KHZ; in tegra_devfreq_update_avg_wmark()
256 u32 band = avg_band_freq * tegra->devfreq->profile->polling_ms; in tegra_devfreq_update_avg_wmark()
266 static void tegra_devfreq_update_wmark(struct tegra_devfreq *tegra, in tegra_devfreq_update_wmark() argument
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/Linux-v5.15/drivers/ata/
Dahci_tegra.c20 #include <soc/tegra/fuse.h>
21 #include <soc/tegra/pmc.h>
25 #define DRV_NAME "tegra-ahci"
184 struct tegra_ahci_priv *tegra = hpriv->plat_data; in tegra_ahci_handle_quirks() local
187 if (tegra->sata_aux_regs && !tegra->soc->supports_devslp) { in tegra_ahci_handle_quirks()
188 val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); in tegra_ahci_handle_quirks()
190 writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); in tegra_ahci_handle_quirks()
196 struct tegra_ahci_priv *tegra = hpriv->plat_data; in tegra124_ahci_init() local
208 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); in tegra124_ahci_init()
210 val = readl(tegra->sata_regs + in tegra124_ahci_init()
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/Linux-v5.15/drivers/clk/tegra/
Dclk-tegra124-emc.c3 * drivers/clk/tegra/clk-emc.c
14 #include <linux/clk/tegra.h>
25 #include <soc/tegra/fuse.h>
94 struct tegra_clk_emc *tegra; in emc_recalc_rate() local
97 tegra = container_of(hw, struct tegra_clk_emc, hw); in emc_recalc_rate()
105 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()
118 struct tegra_clk_emc *tegra; in emc_determine_rate() local
123 tegra = container_of(hw, struct tegra_clk_emc, hw); in emc_determine_rate()
125 for (k = 0; k < tegra->num_timings; k++) { in emc_determine_rate()
126 if (tegra->timings[k].ram_code == ram_code) in emc_determine_rate()
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/Linux-v5.15/drivers/soc/tegra/
Dregulators-tegra20.c10 #define pr_fmt(fmt) "tegra voltage-coupler: " fmt
20 #include <soc/tegra/pmc.h>
39 static int tegra20_core_limit(struct tegra_regulator_coupler *tegra, in tegra20_core_limit() argument
57 if (tegra_pmc_core_domain_state_synced() && !tegra->sys_reboot_mode) { in tegra20_core_limit()
62 if (tegra->core_min_uV > 0) in tegra20_core_limit()
63 return tegra->core_min_uV; in tegra20_core_limit()
80 tegra->core_min_uV = core_max_uV; in tegra20_core_limit()
82 pr_info("core voltage initialized to %duV\n", tegra->core_min_uV); in tegra20_core_limit()
84 return tegra->core_min_uV; in tegra20_core_limit()
108 static int tegra20_core_rtc_update(struct tegra_regulator_coupler *tegra, in tegra20_core_rtc_update() argument
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Dregulators-tegra30.c10 #define pr_fmt(fmt) "tegra voltage-coupler: " fmt
20 #include <soc/tegra/fuse.h>
21 #include <soc/tegra/pmc.h>
39 static int tegra30_core_limit(struct tegra_regulator_coupler *tegra, in tegra30_core_limit() argument
57 if (tegra_pmc_core_domain_state_synced() && !tegra->sys_reboot_mode) { in tegra30_core_limit()
62 if (tegra->core_min_uV > 0) in tegra30_core_limit()
63 return tegra->core_min_uV; in tegra30_core_limit()
80 tegra->core_min_uV = core_max_uV; in tegra30_core_limit()
82 pr_info("core voltage initialized to %duV\n", tegra->core_min_uV); in tegra30_core_limit()
84 return tegra->core_min_uV; in tegra30_core_limit()
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/Linux-v5.15/drivers/thermal/tegra/
Dtegra-bpmp-thermal.c16 #include <soc/tegra/bpmp.h>
17 #include <soc/tegra/bpmp-abi.h>
20 struct tegra_bpmp_thermal *tegra; member
52 err = tegra_bpmp_transfer(zone->tegra->bpmp, &msg); in tegra_bpmp_thermal_get_temp()
79 return tegra_bpmp_transfer(zone->tegra->bpmp, &msg); in tegra_bpmp_thermal_set_trips()
96 struct tegra_bpmp_thermal *tegra = data; in bpmp_mrq_thermal() local
102 dev_err(tegra->dev, "%s: invalid request type: %d\n", in bpmp_mrq_thermal()
108 for (i = 0; i < tegra->num_zones; ++i) { in bpmp_mrq_thermal()
109 if (tegra->zones[i]->idx != req->host_trip_reached.zone) in bpmp_mrq_thermal()
112 schedule_work(&tegra->zones[i]->tz_device_update_work); in bpmp_mrq_thermal()
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DMakefile2 obj-$(CONFIG_TEGRA_SOCTHERM) += tegra-soctherm.o
3 obj-$(CONFIG_TEGRA_BPMP_THERMAL) += tegra-bpmp-thermal.o
6 tegra-soctherm-y := soctherm.o soctherm-fuse.o
7 tegra-soctherm-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124-soctherm.o
8 tegra-soctherm-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-soctherm.o
9 tegra-soctherm-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-soctherm.o
/Linux-v5.15/drivers/gpu/drm/tegra/
Ddrm.c29 #define DRIVER_NAME "tegra"
30 #define DRIVER_DESC "NVIDIA Tegra graphics"
74 struct tegra_drm *tegra = drm->dev_private; in tegra_atomic_commit_tail() local
76 if (tegra->hub) { in tegra_atomic_commit_tail()
450 struct tegra_drm *tegra = drm->dev_private; in tegra_open_channel() local
462 list_for_each_entry(client, &tegra->clients, list) in tegra_open_channel()
844 struct tegra_drm *tegra = drm->dev_private; in tegra_debugfs_iova() local
847 if (tegra->domain) { in tegra_debugfs_iova()
848 mutex_lock(&tegra->mm_lock); in tegra_debugfs_iova()
849 drm_mm_print(&tegra->mm, &p); in tegra_debugfs_iova()
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/Linux-v5.15/sound/soc/tegra/
DKconfig3 tristate "SoC Audio for the Tegra System-on-Chip"
10 Say Y or M here if you want support for SoC audio on Tegra.
112 tristate "Audio Graph Card based Tegra driver"
115 Config to enable Tegra audio machine driver based on generic
117 few things for Tegra audio. Most of the code is re-used from
124 tristate "SoC Audio support for Tegra boards using an RT5640 codec"
129 Say Y or M here if you want to add support for SoC audio on Tegra
133 tristate "SoC Audio support for Tegra boards using a WM8753 codec"
138 Say Y or M here if you want to add support for SoC audio on Tegra
142 tristate "SoC Audio support for Tegra boards using a WM8903 codec"
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DMakefile2 # Tegra platform Support
3 snd-soc-tegra-pcm-objs := tegra_pcm.o
4 snd-soc-tegra-utils-objs += tegra_asoc_utils.o
17 obj-$(CONFIG_SND_SOC_TEGRA) += snd-soc-tegra-pcm.o
30 # Tegra machine Support
31 snd-soc-tegra-wm8903-objs := tegra_wm8903.o
32 snd-soc-tegra-machine-objs := tegra_asoc_machine.o
33 snd-soc-tegra-audio-graph-card-objs := tegra_audio_graph_card.o
35 obj-$(CONFIG_SND_SOC_TEGRA_WM8903) += snd-soc-tegra-wm8903.o
36 obj-$(CONFIG_SND_SOC_TEGRA_MACHINE_DRV) += snd-soc-tegra-machine.o
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Dtegra_wm8903.c3 * tegra_wm8903.c - Tegra machine ASoC driver for boards using WM8903 codec.
163 { .compatible = "ad,tegra-audio-plutux", .data = &tegra_wm8903_data_legacy },
164 { .compatible = "ad,tegra-audio-wm8903-medcom-wide", .data = &tegra_wm8903_data_legacy },
165 { .compatible = "ad,tegra-audio-wm8903-tec", .data = &tegra_wm8903_data_legacy },
166 { .compatible = "nvidia,tegra-audio-wm8903-cardhu", .data = &tegra_wm8903_data_legacy },
167 { .compatible = "nvidia,tegra-audio-wm8903-harmony", .data = &tegra_wm8903_data_legacy },
168 { .compatible = "nvidia,tegra-audio-wm8903-picasso", .data = &tegra_wm8903_data_legacy },
169 { .compatible = "nvidia,tegra-audio-wm8903-seaboard", .data = &tegra_wm8903_data_legacy },
170 { .compatible = "nvidia,tegra-audio-wm8903-ventana", .data = &tegra_wm8903_data_legacy },
171 { .compatible = "nvidia,tegra-audio-wm8903", .data = &tegra_wm8903_data },
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/Linux-v5.15/drivers/memory/tegra/
DMakefile2 tegra-mc-y := mc.o
4 tegra-mc-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20.o
5 tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o
6 tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o
7 tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
8 tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o
9 tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
10 tegra-mc-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o
11 tegra-mc-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o tegra194.o
13 obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
/Linux-v5.15/drivers/firmware/tegra/
DMakefile2 tegra-bpmp-y = bpmp.o
3 tegra-bpmp-$(CONFIG_ARCH_TEGRA_210_SOC) += bpmp-tegra210.o
4 tegra-bpmp-$(CONFIG_ARCH_TEGRA_186_SOC) += bpmp-tegra186.o
5 tegra-bpmp-$(CONFIG_ARCH_TEGRA_194_SOC) += bpmp-tegra186.o
6 tegra-bpmp-$(CONFIG_ARCH_TEGRA_234_SOC) += bpmp-tegra186.o
7 tegra-bpmp-$(CONFIG_DEBUG_FS) += bpmp-debugfs.o
8 obj-$(CONFIG_TEGRA_BPMP) += tegra-bpmp.o
/Linux-v5.15/drivers/phy/tegra/
DMakefile2 obj-$(CONFIG_PHY_TEGRA_XUSB) += phy-tegra-xusb.o
4 phy-tegra-xusb-y += xusb.o
5 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_124_SOC) += xusb-tegra124.o
6 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_132_SOC) += xusb-tegra124.o
7 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_210_SOC) += xusb-tegra210.o
8 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_186_SOC) += xusb-tegra186.o
9 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_194_SOC) += xusb-tegra186.o
/Linux-v5.15/Documentation/devicetree/bindings/sound/
Dnvidia,tegra-audio-trimslice.txt1 NVIDIA Tegra audio complex for TrimSlice
4 - compatible : "nvidia,tegra-audio-trimslice"
7 "pll_a" (The Tegra clock of that name),
8 "pll_a_out0" (The Tegra clock of that name),
9 "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
10 - nvidia,i2s-controller : The phandle of the Tegra I2S1 controller
16 compatible = "nvidia,tegra-audio-trimslice";
Dnvidia,tegra-audio-rt5640.txt1 NVIDIA Tegra audio complex, with RT5640 CODEC
4 - compatible : "nvidia,tegra-audio-rt5640"
10 - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
22 - nvidia,i2s-controller : The phandle of the Tegra I2S controller that's
25 assumes that AIF1 on the CODEC is connected to Tegra.
33 compatible = "nvidia,tegra-audio-rt5640-dalmore",
34 "nvidia,tegra-audio-rt5640";
35 nvidia,model = "NVIDIA Tegra Dalmore";
Dnvidia,tegra-audio-wm8753.txt1 NVIDIA Tegra audio complex
4 - compatible : "nvidia,tegra-audio-wm8753"
10 - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
21 - nvidia,i2s-controller : The phandle of the Tegra I2S1 controller
26 compatible = "nvidia,tegra-audio-wm8753-whistler",
27 "nvidia,tegra-audio-wm8753"
28 nvidia,model = "tegra-wm8753-harmony";
Dnvidia,tegra-audio-rt5677.txt1 NVIDIA Tegra audio complex, with RT5677 CODEC
4 - compatible : "nvidia,tegra-audio-rt5677"
10 - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
24 - nvidia,i2s-controller : The phandle of the Tegra I2S controller that's
27 assumes that AIF1 on the CODEC is connected to Tegra.
38 compatible = "nvidia,tegra-audio-rt5677-ryu",
39 "nvidia,tegra-audio-rt5677";
40 nvidia,model = "NVIDIA Tegra Ryu";
Dnvidia,tegra-audio-max98090.txt1 NVIDIA Tegra audio complex, with MAX98090 CODEC
4 - compatible : "nvidia,tegra-audio-max98090"
10 - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
23 - nvidia,i2s-controller : The phandle of the Tegra I2S controller that's
34 compatible = "nvidia,tegra-audio-max98090-venice2",
35 "nvidia,tegra-audio-max98090";
36 nvidia,model = "NVIDIA Tegra Venice2";
Dnvidia,tegra-audio-wm9712.txt1 NVIDIA Tegra audio complex
4 - compatible : "nvidia,tegra-audio-wm9712"
10 - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
39 - nvidia,ac97-controller : The phandle of the Tegra AC97 controller
45 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
46 "nvidia,tegra-audio-wm9712";
/Linux-v5.15/Documentation/gpu/
Dtegra.rst2 drm/tegra NVIDIA Tegra GPU and display driver
5 NVIDIA Tegra SoCs support a set of display, graphics and video functions via
10 Up until, but not including, Tegra124 (aka Tegra K1) the drm/tegra driver
15 The drm/tegra driver supports NVIDIA Tegra SoC generations since Tegra20. It
65 Tegra SoC generations, up until Tegra186 which introduces several changes that
71 Tegra SoCs have two display controllers, each of which can be associated with
100 The type and number of supported outputs varies between Tegra SoC generations.
116 HDMI is supported on all Tegra SoCs. Starting with Tegra210, HDMI is provided
123 Although Tegra has supported DSI since Tegra30, the controller has changed in
126 later are supported by the drm/tegra driver.
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/Linux-v5.15/Documentation/devicetree/bindings/regulator/
Dnvidia,tegra-regulators-coupling.txt1 NVIDIA Tegra Regulators Coupling
4 NVIDIA Tegra SoC's have a mandatory voltage-coupling between regulators.
24 - nvidia,tegra-core-regulator: Boolean property that designates regulator
26 - nvidia,tegra-rtc-regulator: Boolean property that designates regulator
28 - nvidia,tegra-cpu-regulator: Boolean property that designates regulator
42 nvidia,tegra-core-regulator;
52 nvidia,tegra-rtc-regulator;
62 nvidia,tegra-cpu-regulator;
/Linux-v5.15/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-pmc.yaml4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
7 title: Tegra Power Management Controller (PMC)
34 pclk is the Tegra clock of that name and clk32k_in is 32KHz clock
35 input to Tegra.
46 Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
48 Tegra blink pad.
51 See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
139 "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference
173 match the powergates on the Tegra SoC. Each powergate node
174 represents a power-domain on the Tegra SoC that can be power-gated
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/Linux-v5.15/drivers/soc/tegra/fuse/
Dspeedo-tegra30.c10 #include <soc/tegra/fuse.h>
91 pr_debug("Tegra ATE prog ver %d.%d\n", ate_ver/10, ate_ver%10); in fuse_speedo_calib()
143 pr_err("Tegra Unknown pkg %d\n", package_id); in rev_sku_to_speedo_ids()
160 pr_err("Tegra Unknown pkg %d\n", package_id); in rev_sku_to_speedo_ids()
177 pr_err("Tegra Unknown pkg %d\n", package_id); in rev_sku_to_speedo_ids()
214 pr_err("Tegra Unknown pkg %d\n", package_id); in rev_sku_to_speedo_ids()
219 pr_warn("Tegra Unknown SKU %d\n", sku_info->sku_id); in rev_sku_to_speedo_ids()
227 pr_warn("Tegra Unknown chip rev %d\n", sku_info->revision); in rev_sku_to_speedo_ids()
249 pr_debug("Tegra CPU speedo value %u\n", cpu_speedo_val); in tegra30_init_speedo_data()
250 pr_debug("Tegra Core speedo value %u\n", soc_speedo_val); in tegra30_init_speedo_data()
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