Lines Matching full:tegra

3  * drivers/clk/tegra/clk-emc.c
14 #include <linux/clk/tegra.h>
25 #include <soc/tegra/fuse.h>
94 struct tegra_clk_emc *tegra; in emc_recalc_rate() local
97 tegra = container_of(hw, struct tegra_clk_emc, hw); in emc_recalc_rate()
105 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()
118 struct tegra_clk_emc *tegra; in emc_determine_rate() local
123 tegra = container_of(hw, struct tegra_clk_emc, hw); in emc_determine_rate()
125 for (k = 0; k < tegra->num_timings; k++) { in emc_determine_rate()
126 if (tegra->timings[k].ram_code == ram_code) in emc_determine_rate()
130 for (t = k; t < tegra->num_timings; t++) { in emc_determine_rate()
131 if (tegra->timings[t].ram_code != ram_code) in emc_determine_rate()
136 timing = tegra->timings + i; in emc_determine_rate()
143 req->rate = tegra->timings[i - 1].rate; in emc_determine_rate()
165 struct tegra_clk_emc *tegra; in emc_get_parent() local
168 tegra = container_of(hw, struct tegra_clk_emc, hw); in emc_get_parent()
170 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_get_parent()
176 static struct tegra_emc *emc_ensure_emc_driver(struct tegra_clk_emc *tegra) in emc_ensure_emc_driver() argument
180 if (tegra->emc) in emc_ensure_emc_driver()
181 return tegra->emc; in emc_ensure_emc_driver()
183 if (!tegra->prepare_timing_change || !tegra->complete_timing_change) in emc_ensure_emc_driver()
186 if (!tegra->emc_node) in emc_ensure_emc_driver()
189 pdev = of_find_device_by_node(tegra->emc_node); in emc_ensure_emc_driver()
196 of_node_put(tegra->emc_node); in emc_ensure_emc_driver()
197 tegra->emc_node = NULL; in emc_ensure_emc_driver()
199 tegra->emc = platform_get_drvdata(pdev); in emc_ensure_emc_driver()
200 if (!tegra->emc) { in emc_ensure_emc_driver()
205 return tegra->emc; in emc_ensure_emc_driver()
208 static int emc_set_timing(struct tegra_clk_emc *tegra, in emc_set_timing() argument
215 struct tegra_emc *emc = emc_ensure_emc_driver(tegra); in emc_set_timing()
223 if (emc_get_parent(&tegra->hw) == timing->parent_index && in emc_set_timing()
232 tegra->changing_timing = true; in emc_set_timing()
251 err = tegra->prepare_timing_change(emc, timing->rate); in emc_set_timing()
257 spin_lock_irqsave(tegra->lock, flags); in emc_set_timing()
259 car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_set_timing()
267 writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC); in emc_set_timing()
269 spin_unlock_irqrestore(tegra->lock, flags); in emc_set_timing()
271 tegra->complete_timing_change(emc, timing->rate); in emc_set_timing()
273 clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent)); in emc_set_timing()
274 clk_disable_unprepare(tegra->prev_parent); in emc_set_timing()
276 tegra->prev_parent = timing->parent; in emc_set_timing()
277 tegra->changing_timing = false; in emc_set_timing()
288 static struct emc_timing *get_backup_timing(struct tegra_clk_emc *tegra, in get_backup_timing() argument
295 for (i = timing_index+1; i < tegra->num_timings; i++) { in get_backup_timing()
296 timing = tegra->timings + i; in get_backup_timing()
302 tegra->timings[timing_index].parent_index]) in get_backup_timing()
307 timing = tegra->timings + i; in get_backup_timing()
313 tegra->timings[timing_index].parent_index]) in get_backup_timing()
323 struct tegra_clk_emc *tegra; in emc_set_rate() local
328 tegra = container_of(hw, struct tegra_clk_emc, hw); in emc_set_rate()
338 if (tegra->changing_timing) in emc_set_rate()
341 for (i = 0; i < tegra->num_timings; i++) { in emc_set_rate()
342 if (tegra->timings[i].rate == rate && in emc_set_rate()
343 tegra->timings[i].ram_code == ram_code) { in emc_set_rate()
344 timing = tegra->timings + i; in emc_set_rate()
364 backup_timing = get_backup_timing(tegra, i); in emc_set_rate()
373 err = emc_set_timing(tegra, backup_timing); in emc_set_rate()
380 return emc_set_timing(tegra, timing); in emc_set_rate()
385 static int load_one_timing_from_dt(struct tegra_clk_emc *tegra, in load_one_timing_from_dt() argument
441 static int load_timings_from_dt(struct tegra_clk_emc *tegra, in load_timings_from_dt() argument
451 size = (tegra->num_timings + child_count) * sizeof(struct emc_timing); in load_timings_from_dt()
453 tegra->timings = krealloc(tegra->timings, size, GFP_KERNEL); in load_timings_from_dt()
454 if (!tegra->timings) in load_timings_from_dt()
457 timings_ptr = tegra->timings + tegra->num_timings; in load_timings_from_dt()
458 tegra->num_timings += child_count; in load_timings_from_dt()
463 err = load_one_timing_from_dt(tegra, timing, child); in load_timings_from_dt()
488 struct tegra_clk_emc *tegra; in tegra124_clk_register_emc() local
495 tegra = kcalloc(1, sizeof(*tegra), GFP_KERNEL); in tegra124_clk_register_emc()
496 if (!tegra) in tegra124_clk_register_emc()
499 tegra->clk_regs = base; in tegra124_clk_register_emc()
500 tegra->lock = lock; in tegra124_clk_register_emc()
502 tegra->num_timings = 0; in tegra124_clk_register_emc()
514 err = load_timings_from_dt(tegra, node, node_ram_code); in tegra124_clk_register_emc()
521 if (tegra->num_timings == 0) in tegra124_clk_register_emc()
524 tegra->emc_node = of_parse_phandle(np, in tegra124_clk_register_emc()
526 if (!tegra->emc_node) in tegra124_clk_register_emc()
535 tegra->hw.init = &init; in tegra124_clk_register_emc()
537 clk = clk_register(NULL, &tegra->hw); in tegra124_clk_register_emc()
541 tegra->prev_parent = clk_hw_get_parent_by_index( in tegra124_clk_register_emc()
542 &tegra->hw, emc_get_parent(&tegra->hw))->clk; in tegra124_clk_register_emc()
543 tegra->changing_timing = false; in tegra124_clk_register_emc()
546 clk_register_clkdev(clk, "emc", "tegra-clk-debug"); in tegra124_clk_register_emc()
555 struct tegra_clk_emc *tegra; in tegra124_clk_set_emc_callbacks() local
560 tegra = container_of(hw, struct tegra_clk_emc, hw); in tegra124_clk_set_emc_callbacks()
562 tegra->prepare_timing_change = prep_cb; in tegra124_clk_set_emc_callbacks()
563 tegra->complete_timing_change = complete_cb; in tegra124_clk_set_emc_callbacks()
570 struct tegra_clk_emc *tegra = container_of(hw, struct tegra_clk_emc, hw); in tegra124_clk_emc_driver_available() local
572 return tegra->prepare_timing_change && tegra->complete_timing_change; in tegra124_clk_emc_driver_available()