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/Linux-v5.15/arch/arm64/
DKconfig.platforms1 # SPDX-License-Identifier: GPL-2.0-only
9 This enables support for the Actions Semiconductor S900 SoC family.
12 bool "Allwinner sunxi 64-bit SoC Family"
28 Soc family.
31 bool "Apple Silicon SoC family"
34 This enables support for Apple's in-house ARM SoC family, starting
49 This enables support for the Broadcom BCM2837 and BCM2711 SoC.
57 BCM49408 SoCs. These SoCs use Brahma-B53 cores and can be
61 bool "Broadcom iProc SoC Family"
69 bool "Marvell Berlin SoC Family"
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/Linux-v5.15/Documentation/ABI/testing/
Dsysfs-devices-soc5 The /sys/devices/ directory contains a sub-directory for each
6 System-on-Chip (SoC) device on a running platform. Information
7 regarding each SoC can be obtained by reading sysfs files. This
10 The directory created for each SoC will also house information
12 It has been agreed that if an SoC device exists, its supported
13 devices would be better suited to appear as children of that SoC.
19 Read-only attribute common to all SoCs. Contains the SoC machine
26 Read-only attribute common to all SoCs. Contains SoC family name
30 this will contain the JEDEC JEP106 manufacturer’s identification
34 This manufacturer’s identification code is defined by one
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/Linux-v5.15/drivers/pcmcia/
Dsa1111_generic.c1 // SPDX-License-Identifier: GPL-2.0-only
22 #include <asm/mach-types.h>
71 struct sa1111_pcmcia_socket *s = to_skt(skt); in sa1111_pcmcia_socket_state() local
72 u32 status = readl_relaxed(s->dev->mapbase + PCSR); in sa1111_pcmcia_socket_state()
74 switch (skt->nr) { in sa1111_pcmcia_socket_state()
76 state->detect = status & PCSR_S0_DETECT ? 0 : 1; in sa1111_pcmcia_socket_state()
77 state->ready = status & PCSR_S0_READY ? 1 : 0; in sa1111_pcmcia_socket_state()
78 state->bvd1 = status & PCSR_S0_BVD1 ? 1 : 0; in sa1111_pcmcia_socket_state()
79 state->bvd2 = status & PCSR_S0_BVD2 ? 1 : 0; in sa1111_pcmcia_socket_state()
80 state->wrprot = status & PCSR_S0_WP ? 1 : 0; in sa1111_pcmcia_socket_state()
[all …]
/Linux-v5.15/drivers/pinctrl/freescale/
Dpinctrl-mxs.c1 // SPDX-License-Identifier: GPL-2.0+
17 #include "pinctrl-mxs.h"
25 struct mxs_pinctrl_soc_data *soc; member
32 return d->soc->ngroups; in mxs_get_groups_count()
40 return d->soc->groups[group].name; in mxs_get_group_name()
48 *pins = d->soc->groups[group].pins; in mxs_get_group_pins()
49 *num_pins = d->soc->groups[group].npins; in mxs_get_group_pins()
54 static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, in mxs_pin_dbg_show() argument
57 seq_printf(s, " %s", dev_name(pctldev->dev)); in mxs_pin_dbg_show()
69 int length = strlen(np->name) + SUFFIX_LEN; in mxs_dt_node_to_map()
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/Linux-v5.15/arch/arm/mach-at91/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 bool "SAM Cortex-M7 family" if ARM_SINGLE_ARMV7M
17 Select this if you are using an SoC from Microchip's SAME7, SAMS7 or SAMV7
33 Select this if ou are using one of Microchip's SAMA5D2 family SoC.
44 Select this if you are using one of Microchip's SAMA5D3 family SoC.
58 Select this if you are using one of Microchip's SAMA5D4 family SoC.
68 Select this if you are using one of Microchip's SAMA7G5 family SoC.
82 Select this if you are using Microchip's AT91RM9200 SoC.
100 Select this if you are using one of those Microchip SoC:
133 Select this if you are using Microchip's SAM9X60 SoC
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/Linux-v5.15/drivers/phy/samsung/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 tristate "Exynos SoC series Display Port PHY driver"
15 tristate "S5P/Exynos SoC series MIPI CSI-2/DSI PHY driver"
21 Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
29 Enable PCIe PHY support for Exynos SoC series.
33 tristate "SAMSUNG SoC series UFS PHY driver"
51 for particular PHYs will be enabled based on the SoC type in addition
76 particular SoC is compiled in the driver. In case of S5PV210 two phys
77 are available - device and host.
80 tristate "Exynos5 SoC series USB DRD PHY driver"
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/Linux-v5.15/drivers/memory/tegra/
Dmc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
19 #include <soc/tegra/fuse.h>
25 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
28 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
31 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
34 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
37 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
40 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
43 { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc },
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Dtegra20.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <dt-bindings/memory/tegra20-mc.h>
284 spin_lock_irqsave(&mc->lock, flags); in tegra20_mc_hotreset_assert()
286 value = mc_readl(mc, rst->reset); in tegra20_mc_hotreset_assert()
287 mc_writel(mc, value & ~BIT(rst->bit), rst->reset); in tegra20_mc_hotreset_assert()
289 spin_unlock_irqrestore(&mc->lock, flags); in tegra20_mc_hotreset_assert()
300 spin_lock_irqsave(&mc->lock, flags); in tegra20_mc_hotreset_deassert()
302 value = mc_readl(mc, rst->reset); in tegra20_mc_hotreset_deassert()
303 mc_writel(mc, value | BIT(rst->bit), rst->reset); in tegra20_mc_hotreset_deassert()
305 spin_unlock_irqrestore(&mc->lock, flags); in tegra20_mc_hotreset_deassert()
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/Linux-v5.15/drivers/pinctrl/nomadik/
Dpinctrl-abx500.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2013
28 #include <linux/pinctrl/pinconf-generic.h>
31 #include "pinctrl-abx500.h"
34 #include "../pinctrl-utils.h"
82 struct abx500_pinctrl_soc_data *soc; member
98 ret = abx500_get_register_interruptible(pct->dev, in abx500_gpio_get_bit()
101 dev_err(pct->dev, in abx500_gpio_get_bit()
102 "%s read reg =%x, offset=%x failed (%d)\n", in abx500_gpio_get_bit()
120 ret = abx500_mask_and_set_register_interruptible(pct->dev, in abx500_gpio_set_bits()
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/Linux-v5.15/drivers/phy/tegra/
Dxusb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
20 #include <soc/tegra/fuse.h>
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate()
[all …]
/Linux-v5.15/drivers/soc/fsl/
Dguts.c1 // SPDX-License-Identifier: GPL-2.0-or-later
34 /* SoC die attribute definition for QorIQ platform */
37 * Power Architecture-based SoCs T Series
40 /* Die: T4240, SoC: T4240/T4160/T4080 */
45 /* Die: T1040, SoC: T1040/T1020/T1042/T1022 */
50 /* Die: T2080, SoC: T2080/T2081 */
55 /* Die: T1024, SoC: T1024/T1014/T1023/T1013 */
62 * ARM-based SoCs LS Series
65 /* Die: LS1043A, SoC: LS1043A/LS1023A */
70 /* Die: LS2080A, SoC: LS2080A/LS2040A/LS2085A */
[all …]
/Linux-v5.15/sound/soc/fsl/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "SoC Audio for Freescale CPUs"
4 comment "Common SoC Audio options for Freescale CPUs:"
14 This option is only useful for out-of-tree drivers since
15 in-tree drivers select it automatically.
25 This option is only useful for out-of-tree drivers since
26 in-tree drivers select it automatically.
35 This option is only useful for out-of-tree drivers since
36 in-tree drivers select it automatically.
53 This option is only useful for out-of-tree drivers since
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/Linux-v5.15/drivers/pinctrl/mvebu/
Dpinctrl-mvebu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
24 #include "pinctrl-mvebu.h"
64 *config = (readl(data->base + off) >> shift) & MVEBU_MPP_MASK; in mvebu_mmio_mpp_ctrl_get()
76 reg = readl(data->base + off) & ~(MVEBU_MPP_MASK << shift); in mvebu_mmio_mpp_ctrl_set()
77 writel(reg | (config << shift), data->base + off); in mvebu_mmio_mpp_ctrl_set()
86 for (n = 0; n < pctl->num_groups; n++) { in mvebu_pinctrl_find_group_by_pid()
87 if (pid >= pctl->groups[n].pins[0] && in mvebu_pinctrl_find_group_by_pid()
88 pid < pctl->groups[n].pins[0] + in mvebu_pinctrl_find_group_by_pid()
89 pctl->groups[n].npins) in mvebu_pinctrl_find_group_by_pid()
[all …]
/Linux-v5.15/drivers/pinctrl/tegra/
Dpinctrl-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
10 * Copyright (C) 2009-2011 ST-Ericsson AB
25 #include "../pinctrl-utils.h"
26 #include "pinctrl-tegra.h"
30 return readl(pmx->regs[bank] + reg); in pmx_readl()
35 writel_relaxed(val, pmx->regs[bank] + reg); in pmx_writel()
44 return pmx->soc->ngroups; in tegra_pinctrl_get_groups_count()
52 return pmx->soc->groups[group].name; in tegra_pinctrl_get_group_name()
62 *pins = pmx->soc->groups[group].pins; in tegra_pinctrl_get_group_pins()
[all …]
/Linux-v5.15/drivers/iommu/
Dtegra-smmu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-2014 NVIDIA CORPORATION. All rights reserved.
17 #include <linux/dma-mapping.h>
19 #include <soc/tegra/ahb.h>
20 #include <soc/tegra/mc.h>
25 const struct tegra_smmu_group_soc *soc; member
35 const struct tegra_smmu_soc *soc; member
73 writel(value, smmu->regs + offset); in smmu_writel()
78 return readl(smmu->regs + offset); in smmu_readl()
88 ((smmu)->soc->num_tlb_lines & (smmu)->tlb_mask)
[all …]
/Linux-v5.15/drivers/bus/
Dmvebu-mbus.c14 * - One to configure the access of the CPU to the devices. Depending
20 * - One to configure the access to the CPU to the SDRAM. There are
26 * - Reads out the SDRAM address decoding windows at initialization
33 * devices have to configure those device -> SDRAM windows to ensure
36 * - Provides an API for platform code or device drivers to
37 * dynamically add or remove address decoding windows for the CPU ->
42 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
43 * see the list of CPU -> SDRAM windows and their configuration
44 * (file 'sdram') and the list of CPU -> devices windows and their
118 void (*setup_cpu_target)(struct mvebu_mbus_state *s);
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/Linux-v5.15/drivers/pinctrl/qcom/
Dpinctrl-msm.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/soc/qcom/irq.h>
31 #include "pinctrl-msm.h"
32 #include "../pinctrl-utils.h"
39 * struct msm_pinctrl - state for a pinctrl-msm device
55 * @soc: Reference to soc_data of platform specific data.
78 const struct msm_pinctrl_soc_data *soc; member
87 return readl(pctrl->regs[g->tile] + g->name##_reg); \
92 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
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/Linux-v5.15/sound/soc/atmel/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "SoC Audio for the Atmel System-on-Chip"
25 tristate "SoC PCM DAI support for AT91 SSC controller using PDC"
31 in PDC mode configured using audio-graph-card in device-tree.
34 tristate "SoC PCM DAI support for AT91 SSC controller using DMA"
40 in DMA mode configured using audio-graph-card in device-tree.
43 tristate "SoC Audio support for WM8731-based At91sam9g20 evaluation board"
49 Say Y if you want to add support for SoC audio on WM8731-based
63 tristate "SoC Audio support for WM8731-based at91sam9x5 board"
69 Say Y if you want to add support for audio SoC on an
[all …]
/Linux-v5.15/drivers/thermal/tegra/
Dsoctherm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014 - 2018, NVIDIA CORPORATION. All rights reserved.
34 #include <dt-bindings/thermal/tegra124-soctherm.h>
197 #define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
200 (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
203 #define THROT_DEPTH_DIVIDEND(depth) ((256 * (100 - (depth)) / 100) - 1)
205 /* gk20a nv_therm interface N:3 Mapping. Levels defined in tegra124-soctherm.h
212 #define THROT_LEVEL_TO_DEPTH(level) ((0x1 << (level)) - 1)
229 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
232 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/power/reset/
Dkeystone-reset.txt3 This node is intended to allow SoC reset in case of software reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
14 - compatible: ti,keystone-reset
16 - ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
20 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
26 - ti,soft-reset: Boolean option indicating soft reset.
29 - ti,wdt-list: WDT list that can cause SoC reset. It's not related
30 to WDT driver, it's just needed to enable a SoC related
31 reset that's triggered by one of WDTs. The list is
33 begins from 0 to 3, as keystone can contain up to 4 SoC
[all …]
/Linux-v5.15/sound/soc/samsung/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
45 tristate "SoC I2S Audio support for Jive"
50 Say Y if you want to add support for SoC audio on the Jive.
53 tristate "SoC I2S Audio support for WM8580 on SMDK"
59 Say Y if you want to add support for SoC audio on the SMDKs.
62 tristate "SoC I2S Audio support for WM8994 on SMDK"
68 Say Y if you want to add support for SoC audio on the SMDKs.
71 tristate "SoC I2S Audio support UDA134X wired to a S3C24XX"
83 tristate "SoC I2S Audio support for TLV320AIC23 on Simtec boards"
90 tristate "SoC I2S Audio support for Simtec Hermes board"
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/pinctrl/
Dfsl,imx-pinctrl.txt10 Please refer to pinctrl-bindings.txt in this directory for details of the
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
25 - fsl,pins: each entry consists of 6 integers and represents the mux and config
28 imx*-pinfunc.h under device tree source folder. The last integer CONFIG is
29 the pad setting value like pull-up on this pin. And that's why fsl,pins entry
41 Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
45 Some requirements for using fsl,imx-pinctrl binding:
47 what pinmux functions this SoC supports.
[all …]
/Linux-v5.15/drivers/net/mdio/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 loadable module or built-in.
54 interface units of the Allwinner SoC that have an EMAC (A10,
58 tristate "APM X-Gene SoC MDIO bus controller"
62 APM X-Gene SoC's.
70 controllers found in the ASPEED AST2600 SoC. This is a driver for the
71 third revision of the ASPEED MDIO register interface - the first two
93 Broadcom iProc SoC's.
108 tristate "GPIO lib-based bitbanged MDIO buses"
112 Supports GPIO lib-based MDIO busses.
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/ptp/
Dbrcm,ptp-dte.txt4 - compatible: should contain the core compatibility string
5 and the SoC compatibility string. The SoC
6 compatibility string is to handle SoC specific
9 "brcm,ptp-dte"
10 SoC compatibility strings:
11 "brcm,iproc-ptp-dte" - for iproc based SoC's
12 - reg: address and length of the DTE block's NCO registers
16 ptp: ptp-dte@180af650 {
17 compatible = "brcm,iproc-ptp-dte", "brcm,ptp-dte";
/Linux-v5.15/drivers/clk/tegra/
Dclk-dfll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * clk-dfll.c - Tegra DFLL clock source common code
5 * Copyright (C) 2012-2019 NVIDIA Corporation. All rights reserved.
11 * SoC. These IP blocks together are also known at NVIDIA as
12 * "CL-DVFS". To try to avoid confusion, this code refers to them
18 * DFLL can be operated in either open-loop mode or closed-loop mode.
19 * In open-loop mode, the DFLL generates an output clock appropriate
20 * to the supply voltage. In closed-loop mode, when configured with a
25 * variation. In the case of the CPU, it's important to note that the
27 * performance-measurement code and any code that relies on the CPU
[all …]

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