Lines Matching +full:soc +full:- +full:s
1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/soc/qcom/irq.h>
31 #include "pinctrl-msm.h"
32 #include "../pinctrl-utils.h"
39 * struct msm_pinctrl - state for a pinctrl-msm device
55 * @soc: Reference to soc_data of platform specific data.
78 const struct msm_pinctrl_soc_data *soc; member
87 return readl(pctrl->regs[g->tile] + g->name##_reg); \
92 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
104 u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0; in MSM_ACCESSOR()
113 return pctrl->soc->ngroups; in msm_get_groups_count()
121 return pctrl->soc->groups[group].name; in msm_get_group_name()
131 *pins = pctrl->soc->groups[group].pins; in msm_get_group_pins()
132 *num_pins = pctrl->soc->groups[group].npins; in msm_get_group_pins()
147 struct gpio_chip *chip = &pctrl->chip; in msm_pinmux_request()
149 return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL; in msm_pinmux_request()
156 return pctrl->soc->nfunctions; in msm_get_functions_count()
164 return pctrl->soc->functions[function].name; in msm_get_function_name()
174 *groups = pctrl->soc->functions[function].groups; in msm_get_function_groups()
175 *num_groups = pctrl->soc->functions[function].ngroups; in msm_get_function_groups()
184 struct gpio_chip *gc = &pctrl->chip; in msm_pinmux_set_mux()
185 unsigned int irq = irq_find_mapping(gc->irq.domain, group); in msm_pinmux_set_mux()
187 unsigned int gpio_func = pctrl->soc->gpio_func; in msm_pinmux_set_mux()
193 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
194 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); in msm_pinmux_set_mux()
196 for (i = 0; i < g->nfuncs; i++) { in msm_pinmux_set_mux()
197 if (g->funcs[i] == function) in msm_pinmux_set_mux()
201 if (WARN_ON(i == g->nfuncs)) in msm_pinmux_set_mux()
202 return -EINVAL; in msm_pinmux_set_mux()
215 !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux)) in msm_pinmux_set_mux()
218 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_pinmux_set_mux()
222 val |= i << g->mux_bit; in msm_pinmux_set_mux()
225 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_pinmux_set_mux()
228 test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) { in msm_pinmux_set_mux()
233 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_pinmux_set_mux()
249 const struct msm_pingroup *g = &pctrl->soc->groups[offset]; in msm_pinmux_request_gpio()
252 if (!g->nfuncs) in msm_pinmux_request_gpio()
255 return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset); in msm_pinmux_request_gpio()
278 *bit = g->pull_bit; in msm_config_reg()
282 *bit = g->od_bit; in msm_config_reg()
286 *bit = g->drv_bit; in msm_config_reg()
291 *bit = g->oe_bit; in msm_config_reg()
295 return -ENOTSUPP; in msm_config_reg()
325 g = &pctrl->soc->groups[group]; in msm_config_group_get()
338 return -EINVAL; in msm_config_group_get()
343 return -EINVAL; in msm_config_group_get()
347 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
348 return -ENOTSUPP; in msm_config_group_get()
351 return -EINVAL; in msm_config_group_get()
355 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
360 return -EINVAL; in msm_config_group_get()
363 /* Pin is not open-drain */ in msm_config_group_get()
365 return -EINVAL; in msm_config_group_get()
374 return -EINVAL; in msm_config_group_get()
377 arg = !!(val & BIT(g->in_bit)); in msm_config_group_get()
382 return -EINVAL; in msm_config_group_get()
386 return -ENOTSUPP; in msm_config_group_get()
410 g = &pctrl->soc->groups[group]; in msm_config_group_set()
429 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
430 return -ENOTSUPP; in msm_config_group_set()
435 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
446 arg = -1; in msm_config_group_set()
448 arg = (arg / 2) - 1; in msm_config_group_set()
452 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
455 val |= BIT(g->out_bit); in msm_config_group_set()
457 val &= ~BIT(g->out_bit); in msm_config_group_set()
459 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
469 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", in msm_config_group_set()
471 return -EINVAL; in msm_config_group_set()
474 /* Range-check user-supplied value */ in msm_config_group_set()
476 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); in msm_config_group_set()
477 return -EINVAL; in msm_config_group_set()
480 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
485 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
504 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_input()
506 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_input()
509 val &= ~BIT(g->oe_bit); in msm_gpio_direction_input()
512 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_input()
524 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_output()
526 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_output()
530 val |= BIT(g->out_bit); in msm_gpio_direction_output()
532 val &= ~BIT(g->out_bit); in msm_gpio_direction_output()
536 val |= BIT(g->oe_bit); in msm_gpio_direction_output()
539 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_output()
550 g = &pctrl->soc->groups[offset]; in msm_gpio_get_direction()
554 return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT : in msm_gpio_get_direction()
564 g = &pctrl->soc->groups[offset]; in msm_gpio_get()
567 return !!(val & BIT(g->in_bit)); in msm_gpio_get()
577 g = &pctrl->soc->groups[offset]; in msm_gpio_set()
579 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_set()
583 val |= BIT(g->out_bit); in msm_gpio_set()
585 val &= ~BIT(g->out_bit); in msm_gpio_set()
588 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_set()
594 static void msm_gpio_dbg_show_one(struct seq_file *s, in msm_gpio_dbg_show_one() argument
625 g = &pctrl->soc->groups[offset]; in msm_gpio_dbg_show_one()
629 is_out = !!(ctl_reg & BIT(g->oe_bit)); in msm_gpio_dbg_show_one()
630 func = (ctl_reg >> g->mux_bit) & 7; in msm_gpio_dbg_show_one()
631 drive = (ctl_reg >> g->drv_bit) & 7; in msm_gpio_dbg_show_one()
632 pull = (ctl_reg >> g->pull_bit) & 3; in msm_gpio_dbg_show_one()
635 val = !!(io_reg & BIT(g->out_bit)); in msm_gpio_dbg_show_one()
637 val = !!(io_reg & BIT(g->in_bit)); in msm_gpio_dbg_show_one()
639 seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in"); in msm_gpio_dbg_show_one()
640 seq_printf(s, " %-4s func%d", val ? "high" : "low", func); in msm_gpio_dbg_show_one()
641 seq_printf(s, " %dmA", msm_regval_to_drive(drive)); in msm_gpio_dbg_show_one()
642 if (pctrl->soc->pull_no_keeper) in msm_gpio_dbg_show_one()
643 seq_printf(s, " %s", pulls_no_keeper[pull]); in msm_gpio_dbg_show_one()
645 seq_printf(s, " %s", pulls_keeper[pull]); in msm_gpio_dbg_show_one()
646 seq_puts(s, "\n"); in msm_gpio_dbg_show_one()
649 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) in msm_gpio_dbg_show() argument
651 unsigned gpio = chip->base; in msm_gpio_dbg_show()
654 for (i = 0; i < chip->ngpio; i++, gpio++) in msm_gpio_dbg_show()
655 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); in msm_gpio_dbg_show()
669 const int *reserved = pctrl->soc->reserved_gpios; in msm_gpio_init_valid_mask()
677 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n"); in msm_gpio_init_valid_mask()
678 return -EINVAL; in msm_gpio_init_valid_mask()
687 len = ret = device_property_count_u16(pctrl->dev, "gpios"); in msm_gpio_init_valid_mask()
692 return -EINVAL; in msm_gpio_init_valid_mask()
696 return -ENOMEM; in msm_gpio_init_valid_mask()
698 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len); in msm_gpio_init_valid_mask()
700 dev_err(pctrl->dev, "could not read list of GPIOs\n"); in msm_gpio_init_valid_mask()
724 /* For dual-edge interrupts in software, since some hardware has no
728 * settings of both-edge irq lines to try and catch the next edge.
731 * - the status bit goes high, indicating that an edge was caught, or
732 * - the input value of the gpio doesn't change during the attempt.
737 * The do-loop tries to sledge-hammer closed the timing hole between
738 * the initial value-read and the polarity-write - if the line value changes
742 * Algorithm comes from Google's msmgpio driver.
753 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
756 pol ^= BIT(g->intr_polarity_bit); in msm_gpio_update_dual_edge_pos()
759 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
763 } while (loop_limit-- > 0); in msm_gpio_update_dual_edge_pos()
764 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", in msm_gpio_update_dual_edge_pos()
776 if (d->parent_data) in msm_gpio_irq_mask()
779 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_mask()
782 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_mask()
784 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_mask()
791 * an irq that it's configured for (either edge for edge type or level in msm_gpio_irq_mask()
792 * for level type irq). The 'non-raw' status enable bit causes the in msm_gpio_irq_mask()
794 * status bit is set. There's a bug though, the edge detection logic in msm_gpio_irq_mask()
801 * enabled all the time causes level interrupts to re-latch into the in msm_gpio_irq_mask()
805 * while it's masked. in msm_gpio_irq_mask()
808 val &= ~BIT(g->intr_raw_status_bit); in msm_gpio_irq_mask()
810 val &= ~BIT(g->intr_enable_bit); in msm_gpio_irq_mask()
813 clear_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_mask()
815 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_mask()
826 if (d->parent_data) in msm_gpio_irq_unmask()
829 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_unmask()
832 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_unmask()
834 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_unmask()
837 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_unmask()
838 val |= BIT(g->intr_enable_bit); in msm_gpio_irq_unmask()
841 set_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_unmask()
843 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_unmask()
851 if (d->parent_data) in msm_gpio_irq_enable()
854 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_enable()
863 if (d->parent_data) in msm_gpio_irq_disable()
866 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_disable()
871 * msm_gpio_update_dual_edge_parent() - Prime next edge for IRQs handled by parent.
876 * different due to what's easy to do with our parent, but in principle it's
883 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_update_dual_edge_parent()
889 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
902 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
912 } while (loop_limit-- > 0); in msm_gpio_update_dual_edge_parent()
913 dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n"); in msm_gpio_update_dual_edge_parent()
923 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_ack()
924 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
929 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_ack()
931 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_ack()
935 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
938 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_ack()
948 pctrl->soc->wakeirq_dual_edge_errata && d->parent_data && in msm_gpio_needs_dual_edge_parent_workaround()
949 test_bit(d->hwirq, pctrl->skip_wake_irqs); in msm_gpio_needs_dual_edge_parent_workaround()
962 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
968 if (d->parent_data) in msm_gpio_irq_set_type()
971 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_set_type()
972 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
977 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_set_type()
979 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_set_type()
984 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) in msm_gpio_irq_set_type()
985 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
987 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
993 if (pctrl->intr_target_use_scm) { in msm_gpio_irq_set_type()
994 u32 addr = pctrl->phys_base[0] + g->intr_target_reg; in msm_gpio_irq_set_type()
999 val &= ~(7 << g->intr_target_bit); in msm_gpio_irq_set_type()
1000 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
1004 dev_err(pctrl->dev, in msm_gpio_irq_set_type()
1006 d->hwirq); in msm_gpio_irq_set_type()
1009 val &= ~(7 << g->intr_target_bit); in msm_gpio_irq_set_type()
1010 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
1020 was_enabled = val & BIT(g->intr_raw_status_bit); in msm_gpio_irq_set_type()
1021 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_set_type()
1022 if (g->intr_detection_width == 2) { in msm_gpio_irq_set_type()
1023 val &= ~(3 << g->intr_detection_bit); in msm_gpio_irq_set_type()
1024 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
1027 val |= 1 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1028 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1031 val |= 2 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1032 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1035 val |= 3 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1036 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1041 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1044 } else if (g->intr_detection_width == 1) { in msm_gpio_irq_set_type()
1045 val &= ~(1 << g->intr_detection_bit); in msm_gpio_irq_set_type()
1046 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
1049 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1050 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1053 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1056 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1057 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1062 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1078 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_set_type()
1081 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_set_type()
1102 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_wake()
1105 return irq_set_irq_wake(pctrl->irq, on); in msm_gpio_irq_set_wake()
1114 if (!try_module_get(gc->owner)) in msm_gpio_irq_reqres()
1115 return -ENODEV; in msm_gpio_irq_reqres()
1117 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq); in msm_gpio_irq_reqres()
1120 msm_gpio_direction_input(gc, d->hwirq); in msm_gpio_irq_reqres()
1122 if (gpiochip_lock_as_irq(gc, d->hwirq)) { in msm_gpio_irq_reqres()
1123 dev_err(gc->parent, in msm_gpio_irq_reqres()
1125 d->hwirq); in msm_gpio_irq_reqres()
1126 ret = -EINVAL; in msm_gpio_irq_reqres()
1131 * The disable / clear-enable workaround we do in msm_pinmux_set_mux() in msm_gpio_irq_reqres()
1135 irq_set_status_flags(d->irq, IRQ_DISABLE_UNLAZY); in msm_gpio_irq_reqres()
1139 module_put(gc->owner); in msm_gpio_irq_reqres()
1147 gpiochip_unlock_as_irq(gc, d->hwirq); in msm_gpio_irq_relres()
1148 module_put(gc->owner); in msm_gpio_irq_relres()
1157 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_affinity()
1168 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_vcpu_affinity()
1187 * Each pin has it's own IRQ status register, so use in msm_gpio_irq_handler()
1190 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { in msm_gpio_irq_handler()
1191 g = &pctrl->soc->groups[i]; in msm_gpio_irq_handler()
1193 if (val & BIT(g->intr_status_bit)) { in msm_gpio_irq_handler()
1194 generic_handle_domain_irq(gc->irq.domain, i); in msm_gpio_irq_handler()
1219 for (i = 0; i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_wakeirq()
1220 map = &pctrl->soc->wakeirq_map[i]; in msm_gpio_wakeirq()
1221 if (map->gpio == child) { in msm_gpio_wakeirq()
1222 *parent = map->wakeirq; in msm_gpio_wakeirq()
1232 if (pctrl->soc->reserved_gpios) in msm_gpio_needs_valid_mask()
1235 return device_property_count_u16(pctrl->dev, "gpios") > 0; in msm_gpio_needs_valid_mask()
1243 unsigned gpio, ngpio = pctrl->soc->ngpios; in msm_gpio_init()
1248 return -EINVAL; in msm_gpio_init()
1250 chip = &pctrl->chip; in msm_gpio_init()
1251 chip->base = -1; in msm_gpio_init()
1252 chip->ngpio = ngpio; in msm_gpio_init()
1253 chip->label = dev_name(pctrl->dev); in msm_gpio_init()
1254 chip->parent = pctrl->dev; in msm_gpio_init()
1255 chip->owner = THIS_MODULE; in msm_gpio_init()
1256 chip->of_node = pctrl->dev->of_node; in msm_gpio_init()
1258 chip->init_valid_mask = msm_gpio_init_valid_mask; in msm_gpio_init()
1260 pctrl->irq_chip.name = "msmgpio"; in msm_gpio_init()
1261 pctrl->irq_chip.irq_enable = msm_gpio_irq_enable; in msm_gpio_init()
1262 pctrl->irq_chip.irq_disable = msm_gpio_irq_disable; in msm_gpio_init()
1263 pctrl->irq_chip.irq_mask = msm_gpio_irq_mask; in msm_gpio_init()
1264 pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask; in msm_gpio_init()
1265 pctrl->irq_chip.irq_ack = msm_gpio_irq_ack; in msm_gpio_init()
1266 pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type; in msm_gpio_init()
1267 pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake; in msm_gpio_init()
1268 pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres; in msm_gpio_init()
1269 pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres; in msm_gpio_init()
1270 pctrl->irq_chip.irq_set_affinity = msm_gpio_irq_set_affinity; in msm_gpio_init()
1271 pctrl->irq_chip.irq_set_vcpu_affinity = msm_gpio_irq_set_vcpu_affinity; in msm_gpio_init()
1272 pctrl->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND | in msm_gpio_init()
1276 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0); in msm_gpio_init()
1278 chip->irq.parent_domain = irq_find_matching_host(np, in msm_gpio_init()
1281 if (!chip->irq.parent_domain) in msm_gpio_init()
1282 return -EPROBE_DEFER; in msm_gpio_init()
1283 chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq; in msm_gpio_init()
1284 pctrl->irq_chip.irq_eoi = irq_chip_eoi_parent; in msm_gpio_init()
1286 * Let's skip handling the GPIOs, if the parent irqchip in msm_gpio_init()
1289 skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain); in msm_gpio_init()
1290 for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_init()
1291 gpio = pctrl->soc->wakeirq_map[i].gpio; in msm_gpio_init()
1292 set_bit(gpio, pctrl->skip_wake_irqs); in msm_gpio_init()
1296 girq = &chip->irq; in msm_gpio_init()
1297 girq->chip = &pctrl->irq_chip; in msm_gpio_init()
1298 girq->parent_handler = msm_gpio_irq_handler; in msm_gpio_init()
1299 girq->fwnode = pctrl->dev->fwnode; in msm_gpio_init()
1300 girq->num_parents = 1; in msm_gpio_init()
1301 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents), in msm_gpio_init()
1303 if (!girq->parents) in msm_gpio_init()
1304 return -ENOMEM; in msm_gpio_init()
1305 girq->default_type = IRQ_TYPE_NONE; in msm_gpio_init()
1306 girq->handler = handle_bad_irq; in msm_gpio_init()
1307 girq->parents[0] = pctrl->irq; in msm_gpio_init()
1309 ret = gpiochip_add_data(&pctrl->chip, pctrl); in msm_gpio_init()
1311 dev_err(pctrl->dev, "Failed register gpiochip\n"); in msm_gpio_init()
1316 * For DeviceTree-supported systems, the gpio core checks the in msm_gpio_init()
1317 * pinctrl's device node for the "gpio-ranges" property. in msm_gpio_init()
1322 * files which don't set the "gpio-ranges" property or systems that in msm_gpio_init()
1325 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { in msm_gpio_init()
1326 ret = gpiochip_add_pin_range(&pctrl->chip, in msm_gpio_init()
1327 dev_name(pctrl->dev), 0, 0, chip->ngpio); in msm_gpio_init()
1329 dev_err(pctrl->dev, "Failed to add pin range\n"); in msm_gpio_init()
1330 gpiochip_remove(&pctrl->chip); in msm_gpio_init()
1343 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET); in msm_ps_hold_restart()
1352 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL); in msm_ps_hold_poweroff()
1358 const struct msm_function *func = pctrl->soc->functions; in msm_pinctrl_setup_pm_reset()
1360 for (i = 0; i < pctrl->soc->nfunctions; i++) in msm_pinctrl_setup_pm_reset()
1362 pctrl->restart_nb.notifier_call = msm_ps_hold_restart; in msm_pinctrl_setup_pm_reset()
1363 pctrl->restart_nb.priority = 128; in msm_pinctrl_setup_pm_reset()
1364 if (register_restart_handler(&pctrl->restart_nb)) in msm_pinctrl_setup_pm_reset()
1365 dev_err(pctrl->dev, in msm_pinctrl_setup_pm_reset()
1377 return pinctrl_force_sleep(pctrl->pctrl); in msm_pinctrl_suspend()
1384 return pinctrl_force_default(pctrl->pctrl); in msm_pinctrl_resume()
1400 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in msm_pinctrl_probe()
1402 return -ENOMEM; in msm_pinctrl_probe()
1404 pctrl->dev = &pdev->dev; in msm_pinctrl_probe()
1405 pctrl->soc = soc_data; in msm_pinctrl_probe()
1406 pctrl->chip = msm_gpio_template; in msm_pinctrl_probe()
1407 pctrl->intr_target_use_scm = of_device_is_compatible( in msm_pinctrl_probe()
1408 pctrl->dev->of_node, in msm_pinctrl_probe()
1409 "qcom,ipq8064-pinctrl"); in msm_pinctrl_probe()
1411 raw_spin_lock_init(&pctrl->lock); in msm_pinctrl_probe()
1413 if (soc_data->tiles) { in msm_pinctrl_probe()
1414 for (i = 0; i < soc_data->ntiles; i++) { in msm_pinctrl_probe()
1416 soc_data->tiles[i]); in msm_pinctrl_probe()
1417 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res); in msm_pinctrl_probe()
1418 if (IS_ERR(pctrl->regs[i])) in msm_pinctrl_probe()
1419 return PTR_ERR(pctrl->regs[i]); in msm_pinctrl_probe()
1423 pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res); in msm_pinctrl_probe()
1424 if (IS_ERR(pctrl->regs[0])) in msm_pinctrl_probe()
1425 return PTR_ERR(pctrl->regs[0]); in msm_pinctrl_probe()
1427 pctrl->phys_base[0] = res->start; in msm_pinctrl_probe()
1432 pctrl->irq = platform_get_irq(pdev, 0); in msm_pinctrl_probe()
1433 if (pctrl->irq < 0) in msm_pinctrl_probe()
1434 return pctrl->irq; in msm_pinctrl_probe()
1436 pctrl->desc.owner = THIS_MODULE; in msm_pinctrl_probe()
1437 pctrl->desc.pctlops = &msm_pinctrl_ops; in msm_pinctrl_probe()
1438 pctrl->desc.pmxops = &msm_pinmux_ops; in msm_pinctrl_probe()
1439 pctrl->desc.confops = &msm_pinconf_ops; in msm_pinctrl_probe()
1440 pctrl->desc.name = dev_name(&pdev->dev); in msm_pinctrl_probe()
1441 pctrl->desc.pins = pctrl->soc->pins; in msm_pinctrl_probe()
1442 pctrl->desc.npins = pctrl->soc->npins; in msm_pinctrl_probe()
1444 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); in msm_pinctrl_probe()
1445 if (IS_ERR(pctrl->pctrl)) { in msm_pinctrl_probe()
1446 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); in msm_pinctrl_probe()
1447 return PTR_ERR(pctrl->pctrl); in msm_pinctrl_probe()
1456 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); in msm_pinctrl_probe()
1466 gpiochip_remove(&pctrl->chip); in msm_pinctrl_remove()
1468 unregister_restart_handler(&pctrl->restart_nb); in msm_pinctrl_remove()