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Searched full:rx_clk (Results 1 – 19 of 19) sorted by relevance

/Linux-v6.1/arch/arm64/boot/dts/xilinx/
Dzynqmp-clk-ccf.dtsi138 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
145 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
152 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
159 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
/Linux-v6.1/Documentation/devicetree/bindings/net/
Dqcom-emac.txt44 "mdio_clk", "tx_clk", "rx_clk", "sys_clk";
93 "mdio_clk", "tx_clk", "rx_clk", "sys_clk";
Dcdns,macb.yaml83 - enum: [ rx_clk, tsu_clk ]
199 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
Dqca,ar803x.yaml47 cable is disconnected. And the RX_CLK always keeps outputting a
/Linux-v6.1/drivers/dma/xilinx/
Dxilinx_dma.c473 struct clk **rx_clk, struct clk **rxs_clk);
491 * @rx_clk: DMA s2mm clock
509 struct clk *rx_clk; member
2577 struct clk **tx_clk, struct clk **rx_clk, in axidma_clk_init() argument
2592 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk"); in axidma_clk_init()
2593 if (IS_ERR(*rx_clk)) in axidma_clk_init()
2594 *rx_clk = NULL; in axidma_clk_init()
2612 err = clk_prepare_enable(*rx_clk); in axidma_clk_init()
2614 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err); in axidma_clk_init()
2627 clk_disable_unprepare(*rx_clk); in axidma_clk_init()
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/Linux-v6.1/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-meson8b.c61 * cleared on both, the falling and rising edge of the RX_CLK. This selects the
73 /* Defined for adding a delay to the input RX_CLK for better timing.
76 * adjust the window between RX_CLK and RX_DATA and improve the stability
/Linux-v6.1/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
Dpincfg.txt52 0 0 2 0 1 0 /* RX_CLK */
/Linux-v6.1/drivers/net/ethernet/cadence/
Dmacb_main.c3861 struct clk *rx_clk, struct clk *tsu_clk) in macb_clks_disable() argument
3865 { .clk = rx_clk, }, in macb_clks_disable()
3876 struct clk **rx_clk, struct clk **tsu_clk) in macb_clk_init() argument
3904 *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk"); in macb_clk_init()
3905 if (IS_ERR(*rx_clk)) in macb_clk_init()
3906 return PTR_ERR(*rx_clk); in macb_clk_init()
3930 err = clk_prepare_enable(*rx_clk); in macb_clk_init()
3932 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err); in macb_clk_init()
3945 clk_disable_unprepare(*rx_clk); in macb_clk_init()
4454 struct clk **rx_clk, struct clk **tsu_clk) in at91ether_clk_init() argument
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Dmacb.h1183 struct clk **rx_clk, struct clk **tsu_clk);
1267 struct clk *rx_clk; member
/Linux-v6.1/arch/powerpc/boot/dts/fsl/
Dmpc8568mds.dts148 0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
176 0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
/Linux-v6.1/arch/powerpc/boot/dts/
Dmpc832x_rdb.dts179 3 21 2 0 1 0 /* RX_CLK (CLK16) */
199 0 13 2 0 1 0 /* RX_CLK (CLK9) */
Dmpc832x_mds.dts191 0 13 2 0 1 0 /* RX_CLK (CLK9) */
211 3 31 2 0 1 0 /* RX_CLK (CLK7) */
Dmpc836x_mds.dts250 0 0 2 0 1 0 /* RX_CLK */
277 0 31 2 0 1 0 /* RX_CLK */
Dkmeter1.dts163 0 0 2 0 1 0 /* RX_CLK */
189 0 31 2 0 1 0 /* RX_CLK */
/Linux-v6.1/drivers/net/phy/
Dmicrel.c864 /* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of
870 /* set rx to +0.30ns and rx_clk to -0.90ns to compensate the
962 u16 rx, tx, rx_clk, tx_clk; in ksz9031_config_rgmii_delay() local
970 rx_clk = RX_CLK_ND; in ksz9031_config_rgmii_delay()
976 rx_clk = RX_CLK_ID; in ksz9031_config_rgmii_delay()
982 rx_clk = RX_CLK_ID; in ksz9031_config_rgmii_delay()
988 rx_clk = RX_CLK_ND; in ksz9031_config_rgmii_delay()
1018 FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk)); in ksz9031_config_rgmii_delay()
Dicplus.c35 #define IP1001_RXPHASE_SEL BIT(0) /* Add delay on RX_CLK */
/Linux-v6.1/drivers/net/dsa/sja1105/
Dsja1105_clocking.c444 pad_mii_rx.clk_os = 2; /* RX_CLK/RXC output stage: */ in sja1105_cfg_pad_rx_config()
446 pad_mii_rx.clk_ih = 0; /* RX_CLK/RXC input hysteresis: */ in sja1105_cfg_pad_rx_config()
448 pad_mii_rx.clk_ipud = 2; /* RX_CLK/RXC input pull-up/down: */ in sja1105_cfg_pad_rx_config()
/Linux-v6.1/drivers/net/ethernet/qualcomm/emac/
Demac.c70 "rx_clk", "sys_clk"
/Linux-v6.1/drivers/pinctrl/renesas/
Dpfc-r8a7740.c1917 /* RXD[0:3], RX_CLK, RX_DV, RX_ER
1933 /* RXD[0:7], RX_CLK, RX_DV, RX_ER