Home
last modified time | relevance | path

Searched full:rw (Results 1 – 25 of 892) sorted by relevance

12345678910>>...36

/Linux-v5.10/arch/x86/include/asm/uv/
Duv_mmrs.h555 unsigned long lb_hcerr:1; /* RW */
561 unsigned long lb_hcerr:1; /* RW */
563 unsigned long rh_hcerr:1; /* RW */
564 unsigned long lh0_hcerr:1; /* RW */
565 unsigned long lh1_hcerr:1; /* RW */
566 unsigned long gr0_hcerr:1; /* RW */
567 unsigned long gr1_hcerr:1; /* RW */
568 unsigned long ni0_hcerr:1; /* RW */
569 unsigned long ni1_hcerr:1; /* RW */
570 unsigned long lb_aoerr0:1; /* RW */
[all …]
/Linux-v5.10/drivers/net/wireless/zydas/zd1211rw/
Dzd_rf_rf2959.c32 static int bits(u32 rw, int from, int to)
34 rw &= ~(0xffffffffU << (to+1));
35 rw >>= from;
36 return rw;
39 static int bit(u32 rw, int bit)
41 return bits(rw, bit, bit);
44 static void dump_regwrite(u32 rw)
46 int reg = bits(rw, 18, 22);
47 int rw_flag = bits(rw, 23, 23);
48 PDEBUG("rf2959 %#010x reg %d rw %d", rw, reg, rw_flag);
[all …]
/Linux-v5.10/drivers/gpu/drm/meson/
Dmeson_dw_hdmi.h12 * Bit 15-10: RW Reserved. Default 1 starting from G12A
13 * Bit 9 RW sw_reset_i2c starting from G12A
14 * Bit 8 RW sw_reset_axiarb starting from G12A
15 * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
16 * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
17 * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
18 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
20 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
23 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
25 * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset;
[all …]
/Linux-v5.10/include/linux/mfd/
Dkhadas-mcu.h36 #define KHADAS_MCU_BOOT_MODE_REG 0x20 /* RW */
37 #define KHADAS_MCU_BOOT_EN_WOL_REG 0x21 /* RW */
38 #define KHADAS_MCU_BOOT_EN_RTC_REG 0x22 /* RW */
39 #define KHADAS_MCU_BOOT_EN_EXP_REG 0x23 /* RW */
40 #define KHADAS_MCU_BOOT_EN_IR_REG 0x24 /* RW */
41 #define KHADAS_MCU_BOOT_EN_DCIN_REG 0x25 /* RW */
42 #define KHADAS_MCU_BOOT_EN_KEY_REG 0x26 /* RW */
43 #define KHADAS_MCU_KEY_MODE_REG 0x27 /* RW */
44 #define KHADAS_MCU_LED_MODE_ON_REG 0x28 /* RW */
45 #define KHADAS_MCU_LED_MODE_OFF_REG 0x29 /* RW */
[all …]
Dstmfx.h16 #define STMFX_REG_SYS_CTRL 0x40 /* RW */
18 #define STMFX_REG_IRQ_OUT_PIN 0x41 /* RW */
19 #define STMFX_REG_IRQ_SRC_EN 0x42 /* RW */
21 #define STMFX_REG_IRQ_ACK 0x44 /* RW */
29 #define STMFX_REG_IRQ_GPI_SRC1 0x48 /* RW */
30 #define STMFX_REG_IRQ_GPI_SRC2 0x49 /* RW */
31 #define STMFX_REG_IRQ_GPI_SRC3 0x4A /* RW */
32 #define STMFX_REG_IRQ_GPI_EVT1 0x4C /* RW */
33 #define STMFX_REG_IRQ_GPI_EVT2 0x4D /* RW */
34 #define STMFX_REG_IRQ_GPI_EVT3 0x4E /* RW */
[all …]
/Linux-v5.10/drivers/net/ethernet/intel/e1000e/
Dregs.h7 #define E1000_CTRL 0x00000 /* Device Control - RW */
9 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
10 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
11 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define E1000_FLA 0x0001C /* Flash Access - RW */
13 #define E1000_MDIC 0x00020 /* MDI Control - RW */
14 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
15 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
16 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
17 #define E1000_FEXT 0x0002C /* Future Extended - RW */
[all …]
/Linux-v5.10/drivers/gpu/drm/arm/
Dhdlcd_regs.h16 #define HDLCD_REG_INT_RAWSTAT 0x0010 /* rw */
18 #define HDLCD_REG_INT_MASK 0x0018 /* rw */
20 #define HDLCD_REG_FB_BASE 0x0100 /* rw */
21 #define HDLCD_REG_FB_LINE_LENGTH 0x0104 /* rw */
22 #define HDLCD_REG_FB_LINE_COUNT 0x0108 /* rw */
23 #define HDLCD_REG_FB_LINE_PITCH 0x010c /* rw */
24 #define HDLCD_REG_BUS_OPTIONS 0x0110 /* rw */
25 #define HDLCD_REG_V_SYNC 0x0200 /* rw */
26 #define HDLCD_REG_V_BACK_PORCH 0x0204 /* rw */
27 #define HDLCD_REG_V_DATA 0x0208 /* rw */
[all …]
/Linux-v5.10/drivers/net/ethernet/intel/igb/
De1000_regs.h7 #define E1000_CTRL 0x00000 /* Device Control - RW */
9 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
10 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
11 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define E1000_MDIC 0x00020 /* MDI Control - RW */
13 #define E1000_MDICNFG 0x00E04 /* MDI Config - RW */
14 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
15 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
16 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
17 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
[all …]
/Linux-v5.10/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_reg.h12 * by size in bits. For example [RW 32]. The access types are:
15 * RW - Read/Write
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
38 /* [RW 5] Parity mask register #0 read/write */
44 /* [RW 19] Interrupt mask register #0 read/write */
48 /* [RW 4] Parity mask register #0 read/write */
54 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
62 /* [RW 10] The number of free blocks below which the full signal to class 0
66 /* [RW 11] The number of free blocks above which the full signal to class 0
70 /* [RW 11] The number of free blocks below which the full signal to class 1
[all …]
/Linux-v5.10/arch/ia64/include/asm/uv/
Duv_mmrs.h42 unsigned long vector_ : 8; /* RW */
43 unsigned long dm : 3; /* RW */
44 unsigned long destmode : 1; /* RW */
49 unsigned long m : 1; /* RW */
51 unsigned long apic_id : 32; /* RW */
178 unsigned long lb_hcerr : 1; /* RW, W1C */
179 unsigned long gr0_hcerr : 1; /* RW, W1C */
180 unsigned long gr1_hcerr : 1; /* RW, W1C */
181 unsigned long lh_hcerr : 1; /* RW, W1C */
182 unsigned long rh_hcerr : 1; /* RW, W1C */
[all …]
/Linux-v5.10/arch/parisc/include/asm/
Dspinlock.h67 static inline int arch_read_trylock(arch_rwlock_t *rw) in arch_read_trylock() argument
73 arch_spin_lock(&(rw->lock_mutex)); in arch_read_trylock()
79 if (rw->counter > 0) { in arch_read_trylock()
80 rw->counter--; in arch_read_trylock()
84 arch_spin_unlock(&(rw->lock_mutex)); in arch_read_trylock()
91 static inline int arch_write_trylock(arch_rwlock_t *rw) in arch_write_trylock() argument
97 arch_spin_lock(&(rw->lock_mutex)); in arch_write_trylock()
105 if (rw->counter == __ARCH_RW_LOCK_UNLOCKED__) { in arch_write_trylock()
106 rw->counter = 0; in arch_write_trylock()
109 arch_spin_unlock(&(rw->lock_mutex)); in arch_write_trylock()
[all …]
/Linux-v5.10/arch/arc/include/asm/
Dspinlock.h79 static inline void arch_read_lock(arch_rwlock_t *rw) in arch_read_lock() argument
87 * if (rw->counter > 0) { in arch_read_lock()
88 * rw->counter--; in arch_read_lock()
101 : [rwlock] "r" (&(rw->counter)), in arch_read_lock()
109 static inline int arch_read_trylock(arch_rwlock_t *rw) in arch_read_trylock() argument
125 : [rwlock] "r" (&(rw->counter)), in arch_read_trylock()
134 static inline void arch_write_lock(arch_rwlock_t *rw) in arch_write_lock() argument
144 * if (rw->counter == __ARCH_RW_LOCK_UNLOCKED__) { in arch_write_lock()
145 * rw->counter = 0; in arch_write_lock()
158 : [rwlock] "r" (&(rw->counter)), in arch_write_lock()
[all …]
/Linux-v5.10/drivers/scsi/aic7xxx/
Daic79xx.reg101 access_mode RW
116 access_mode RW
133 access_mode RW
263 access_mode RW
281 access_mode RW
292 access_mode RW
302 access_mode RW
340 access_mode RW
350 access_mode RW
362 access_mode RW
[all …]
/Linux-v5.10/drivers/net/ethernet/intel/igc/
Digc_regs.h8 #define IGC_CTRL 0x00000 /* Device Control - RW */
10 #define IGC_EECD 0x00010 /* EEPROM/Flash Control - RW */
11 #define IGC_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define IGC_MDIC 0x00020 /* MDI Control - RW */
13 #define IGC_MDICNFG 0x00E04 /* MDC/MDIO Configuration - RW */
14 #define IGC_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
18 #define IGC_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
19 #define IGC_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */
22 #define IGC_EERD 0x12014 /* EEprom mode read - RW */
23 #define IGC_EEWR 0x12018 /* EEprom mode write - RW */
[all …]
/Linux-v5.10/Documentation/hwmon/
Damc6821.rst30 temp1_min rw "
31 temp1_max rw "
32 temp1_crit rw "
38 temp2_min rw "
39 temp2_max rw "
40 temp2_crit rw "
47 fan1_min rw "
48 fan1_max rw "
50 fan1_div rw Fan divisor can be either 2 or 4.
52 pwm1 rw pwm1
[all …]
/Linux-v5.10/drivers/char/mwave/
D3780i.h68 unsigned char ClockControl:1; /* RW: Clock control: 0=normal, 1=stop 3780i clocks */
69 unsigned char SoftReset:1; /* RW: Soft reset 0=normal, 1=soft reset active */
70 unsigned char ConfigMode:1; /* RW: Configuration mode, 0=normal, 1=config mode */
76 unsigned short EnableDspInt:1; /* RW: Enable DSP to X86 ISA interrupt 0=mask it, 1=enable it */
77 unsigned short MemAutoInc:1; /* RW: Memory address auto increment, 0=disable, 1=enable */
78 unsigned short IoAutoInc:1; /* RW: I/O address auto increment, 0=disable, 1=enable */
79 unsigned short DiagnosticMode:1; /* RW: Disgnostic mode 0=nromal, 1=diagnostic mode */
96 unsigned char IrqActiveLow:1; /* RW: IRQ active high or low: 0=high, 1=low */
97 unsigned char IrqPulse:1; /* RW: IRQ pulse or level: 0=level, 1=pulse */
98 unsigned char Irq:3; /* RW: IRQ selection */
[all …]
/Linux-v5.10/arch/arm/mach-pxa/
Dpcm990_baseboard.h45 #define PCM990_CTRL_LCDPWR 0x0001 /* RW LCD Power on */
46 #define PCM990_CTRL_LCDON 0x0002 /* RW LCD Latch on */
47 #define PCM990_CTRL_LCDPOS1 0x0004 /* RW POS 1 */
48 #define PCM990_CTRL_LCDPOS2 0x0008 /* RW POS 2 */
51 #define PCM990_CTRL_MMC1PWR 0x0001 /* RW MMC1 Power on */
54 #define PCM990_CTRL_MMC2PWR 0x0001 /* RW MMC2 Power on */
55 #define PCM990_CTRL_MMC2LED 0x0002 /* RW MMC2 LED */
109 #define PCM990_IDE_DMAENA 0x0004 /* RW DMA Enable */
110 #define PCM990_IDE_DMA1_0 0x0008 /* RW 1=DREQ1 0=DREQ0 */
113 #define PCM990_IDE_RESENA 0x0001 /* RW IDE Reset Bit enable */
[all …]
/Linux-v5.10/arch/sh/include/asm/
Dspinlock-cas.h52 static inline void arch_read_lock(arch_rwlock_t *rw) in arch_read_lock() argument
55 do old = rw->lock; in arch_read_lock()
56 while (!old || __sl_cas(&rw->lock, old, old-1) != old); in arch_read_lock()
59 static inline void arch_read_unlock(arch_rwlock_t *rw) in arch_read_unlock() argument
62 do old = rw->lock; in arch_read_unlock()
63 while (__sl_cas(&rw->lock, old, old+1) != old); in arch_read_unlock()
66 static inline void arch_write_lock(arch_rwlock_t *rw) in arch_write_lock() argument
68 while (__sl_cas(&rw->lock, RW_LOCK_BIAS, 0) != RW_LOCK_BIAS); in arch_write_lock()
71 static inline void arch_write_unlock(arch_rwlock_t *rw) in arch_write_unlock() argument
73 __sl_cas(&rw->lock, 0, RW_LOCK_BIAS); in arch_write_unlock()
[all …]
/Linux-v5.10/arch/s390/include/asm/
Dspinlock.h106 #define arch_read_relax(rw) barrier() argument
107 #define arch_write_relax(rw) barrier() argument
112 static inline void arch_read_lock(arch_rwlock_t *rw) in arch_read_lock() argument
116 old = __atomic_add(1, &rw->cnts); in arch_read_lock()
118 arch_read_lock_wait(rw); in arch_read_lock()
121 static inline void arch_read_unlock(arch_rwlock_t *rw) in arch_read_unlock() argument
123 __atomic_add_const_barrier(-1, &rw->cnts); in arch_read_unlock()
126 static inline void arch_write_lock(arch_rwlock_t *rw) in arch_write_lock() argument
128 if (!__atomic_cmpxchg_bool(&rw->cnts, 0, 0x30000)) in arch_write_lock()
129 arch_write_lock_wait(rw); in arch_write_lock()
[all …]
/Linux-v5.10/Documentation/cdrom/
Dpacket-writing.rst16 - Grab a new CD-RW disc and format it (assuming CD-RW is hdc, substitute
27 # mount /dev/pktcdvd/dev_name /cdrom -t udf -o rw,noatime
30 Packet writing for DVD-RW media
33 DVD-RW discs can be written to much like CD-RW discs if they are in
37 # dvd+rw-format /dev/hdc
39 You can then use the disc the same way you would use a CD-RW disc::
42 # mount /dev/pktcdvd/dev_name /cdrom -t udf -o rw,noatime
45 Packet writing for DVD+RW media
48 According to the DVD+RW specification, a drive supporting DVD+RW discs
53 # dvd+rw-format /dev/hdc (only needed if the disc has never
[all …]
/Linux-v5.10/block/
Dblk-throttle.c296 static uint64_t tg_bps_limit(struct throtl_grp *tg, int rw) in tg_bps_limit() argument
306 ret = tg->bps[rw][td->limit_index]; in tg_bps_limit()
310 tg->iops[rw][td->limit_index]) in tg_bps_limit()
316 if (td->limit_index == LIMIT_MAX && tg->bps[rw][LIMIT_LOW] && in tg_bps_limit()
317 tg->bps[rw][LIMIT_LOW] != tg->bps[rw][LIMIT_MAX]) { in tg_bps_limit()
320 adjusted = throtl_adjusted_limit(tg->bps[rw][LIMIT_LOW], td); in tg_bps_limit()
321 ret = min(tg->bps[rw][LIMIT_MAX], adjusted); in tg_bps_limit()
326 static unsigned int tg_iops_limit(struct throtl_grp *tg, int rw) in tg_iops_limit() argument
336 ret = tg->iops[rw][td->limit_index]; in tg_iops_limit()
340 tg->bps[rw][td->limit_index]) in tg_iops_limit()
[all …]
/Linux-v5.10/drivers/media/pci/cx88/
Dcx88-reg.h93 #define MO_DMA7_PTR1 0x300018 // {24}RW* DMA Current Ptr : Ch#7
94 #define MO_DMA8_PTR1 0x30001C // {24}RW* DMA Current Ptr : Ch#8
110 #define MO_DMA21_PTR2 0x3000C0 // {24}RW* DMA Tab Ptr : Ch#21
111 #define MO_DMA22_PTR2 0x3000C4 // {24}RW* DMA Tab Ptr : Ch#22
112 #define MO_DMA23_PTR2 0x3000C8 // {24}RW* DMA Tab Ptr : Ch#23
113 #define MO_DMA24_PTR2 0x3000CC // {24}RW* DMA Tab Ptr : Ch#24
114 #define MO_DMA25_PTR2 0x3000D0 // {24}RW* DMA Tab Ptr : Ch#25
115 #define MO_DMA26_PTR2 0x3000D4 // {24}RW* DMA Tab Ptr : Ch#26
116 #define MO_DMA27_PTR2 0x3000D8 // {24}RW* DMA Tab Ptr : Ch#27
117 #define MO_DMA28_PTR2 0x3000DC // {24}RW* DMA Tab Ptr : Ch#28
[all …]
/Linux-v5.10/drivers/staging/emxx_udc/
Demxx_udc.h255 #define EPN_OUT_END_INT BIT(23) /* RW */
256 #define EPN_OUT_OR_INT BIT(22) /* RW */
257 #define EPN_OUT_NAK_ERR_INT BIT(21) /* RW */
258 #define EPN_OUT_STALL_INT BIT(20) /* RW */
259 #define EPN_OUT_INT BIT(19) /* RW */
260 #define EPN_OUT_NULL_INT BIT(18) /* RW */
267 #define EPN_IN_END_INT BIT(7) /* RW */
269 #define EPN_IN_NAK_ERR_INT BIT(5) /* RW */
270 #define EPN_IN_STALL_INT BIT(4) /* RW */
271 #define EPN_IN_INT BIT(3) /* RW */
[all …]
/Linux-v5.10/drivers/pci/
Dpci-bridge-emul.c30 * @rw: Read-Write bits
43 u32 rw; member
52 .rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
90 /* Primary, secondary and subordinate bus are RW */
91 .rw = GENMASK(24, 0),
97 /* The high four bits of I/O base/limit are RW */
98 .rw = (GENMASK(15, 12) | GENMASK(7, 4)),
109 /* The high 12-bits of mem base/limit are RW */
110 .rw = GENMASK(31, 20) | GENMASK(15, 4),
117 /* The high 12-bits of pref mem base/limit are RW */
[all …]
/Linux-v5.10/kernel/trace/
Dtrace_mmiotrace.c171 struct mmiotrace_rw *rw; in mmio_print_rw() local
178 rw = &field->rw; in mmio_print_rw()
180 switch (rw->opcode) { in mmio_print_rw()
184 rw->width, secs, usec_rem, rw->map_id, in mmio_print_rw()
185 (unsigned long long)rw->phys, in mmio_print_rw()
186 rw->value, rw->pc, 0); in mmio_print_rw()
191 rw->width, secs, usec_rem, rw->map_id, in mmio_print_rw()
192 (unsigned long long)rw->phys, in mmio_print_rw()
193 rw->value, rw->pc, 0); in mmio_print_rw()
199 secs, usec_rem, rw->map_id, in mmio_print_rw()
[all …]

12345678910>>...36