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/Linux-v6.1/arch/riscv/net/
Dbpf_jit.h226 static inline u32 rv_r_insn(u8 funct7, u8 rs2, u8 rs1, u8 funct3, u8 rd, in rv_r_insn() argument
229 return (funct7 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) | in rv_r_insn()
233 static inline u32 rv_i_insn(u16 imm11_0, u8 rs1, u8 funct3, u8 rd, u8 opcode) in rv_i_insn() argument
235 return (imm11_0 << 20) | (rs1 << 15) | (funct3 << 12) | (rd << 7) | in rv_i_insn()
239 static inline u32 rv_s_insn(u16 imm11_0, u8 rs2, u8 rs1, u8 funct3, u8 opcode) in rv_s_insn() argument
243 return (imm11_5 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) | in rv_s_insn()
247 static inline u32 rv_b_insn(u16 imm12_1, u8 rs2, u8 rs1, u8 funct3, u8 opcode) in rv_b_insn() argument
252 return (imm12 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) | in rv_b_insn()
271 static inline u32 rv_amo_insn(u8 funct5, u8 aq, u8 rl, u8 rs2, u8 rs1, in rv_amo_insn() argument
276 return rv_r_insn(funct7, rs2, rs1, funct3, rd, opcode); in rv_amo_insn()
[all …]
Dbpf_jit_comp32.c571 const s8 *rs1 = bpf_get_reg64(src1, tmp1, ctx); in emit_branch_r64() local
587 emit(rv_bne(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); in emit_branch_r64()
588 emit(rv_bne(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); in emit_branch_r64()
591 emit(rv_bgtu(hi(rs1), hi(rs2), JUMP(2)), ctx); in emit_branch_r64()
592 emit(rv_bltu(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); in emit_branch_r64()
593 emit(rv_bleu(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); in emit_branch_r64()
596 emit(rv_bltu(hi(rs1), hi(rs2), JUMP(2)), ctx); in emit_branch_r64()
597 emit(rv_bgtu(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); in emit_branch_r64()
598 emit(rv_bgeu(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); in emit_branch_r64()
601 emit(rv_bgtu(hi(rs1), hi(rs2), JUMP(2)), ctx); in emit_branch_r64()
[all …]
/Linux-v6.1/arch/sparc/kernel/
Dvisemul.c136 #define RS1(INSN) (((INSN) >> 14) & 0x1f) macro
140 static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2, in maybe_flush_windows() argument
143 if (rs2 >= 16 || rs1 >= 16 || rd >= 16) { in maybe_flush_windows()
296 unsigned long orig_rs1, rs1, orig_rs2, rs2, rd_val; in edge() local
299 maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0); in edge()
300 orig_rs1 = rs1 = fetch_reg(RS1(insn), regs); in edge()
304 rs1 = rs1 & 0xffffffff; in edge()
311 left = edge8_tab[rs1 & 0x7].left; in edge()
316 left = edge8_tab_l[rs1 & 0x7].left; in edge()
322 left = edge16_tab[(rs1 >> 1) & 0x3].left; in edge()
[all …]
Dunaligned_32.c72 static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2, in maybe_flush_windows() argument
75 if(rs2 >= 16 || rs1 >= 16 || rd >= 16) { in maybe_flush_windows()
139 unsigned int rs1 = (insn >> 14) & 0x1f; in compute_effective_address() local
144 maybe_flush_windows(rs1, 0, rd); in compute_effective_address()
145 return (fetch_reg(rs1, regs) + sign_extend_imm13(insn)); in compute_effective_address()
147 maybe_flush_windows(rs1, rs2, rd); in compute_effective_address()
148 return (fetch_reg(rs1, regs) + fetch_reg(rs2, regs)); in compute_effective_address()
155 unsigned int rs1 = (insn >> 14) & 0x1f; in safe_compute_effective_address() local
160 maybe_flush_windows(rs1, 0, rd); in safe_compute_effective_address()
161 return (safe_fetch_reg(rs1, regs) + sign_extend_imm13(insn)); in safe_compute_effective_address()
[all …]
Dunaligned_64.c104 static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2, in maybe_flush_windows() argument
107 if (rs2 >= 16 || rs1 >= 16 || rd >= 16) { in maybe_flush_windows()
173 unsigned int rs1 = (insn >> 14) & 0x1f; in compute_effective_address() local
178 maybe_flush_windows(rs1, 0, rd, from_kernel); in compute_effective_address()
179 addr = (fetch_reg(rs1, regs) + sign_extend_imm13(insn)); in compute_effective_address()
181 maybe_flush_windows(rs1, rs2, rd, from_kernel); in compute_effective_address()
182 addr = (fetch_reg(rs1, regs) + fetch_reg(rs2, regs)); in compute_effective_address()
/Linux-v6.1/arch/riscv/include/asm/
Dinsn-def.h19 .macro insn_r, opcode, func3, func7, rd, rs1, rs2
20 .insn r \opcode, \func3, \func7, \rd, \rs1, \rs2
27 .macro insn_r, opcode, func3, func7, rd, rs1, rs2
32 (.L__gpr_num_\rs1 << INSN_R_RS1_SHIFT) | \
44 #define __INSN_R(opcode, func3, func7, rd, rs1, rs2) \
45 ".insn r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n"
54 " .macro insn_r, opcode, func3, func7, rd, rs1, rs2\n" \
59 " (.L__gpr_num_\\rs1 << " __stringify(INSN_R_RS1_SHIFT) ") |" \
66 #define __INSN_R(opcode, func3, func7, rd, rs1, rs2) \
68 "insn_r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n" \
[all …]
Derrata_list.h93 * dcache.ipa rs1 (invalidate, physical address)
95 * 0000001 01010 rs1 000 00000 0001011
96 * dache.iva rs1 (invalida, virtual address)
97 * 0000001 00110 rs1 000 00000 0001011
99 * dcache.cpa rs1 (clean, physical address)
101 * 0000001 01001 rs1 000 00000 0001011
102 * dcache.cva rs1 (clean, virtual address)
103 * 0000001 00100 rs1 000 00000 0001011
105 * dcache.cipa rs1 (clean then invalidate, physical address)
107 * 0000001 01011 rs1 000 00000 0001011
[all …]
Dmodule.h75 * | imm[31:20] | rs1[19:15] | funct3 | rd[11:7] | opc[6:0] | in emit_plt_entry()
/Linux-v6.1/arch/sparc/crypto/
Dopcodes.h11 #define RS1(x) (FPD_ENCODE(x) << 14) macro
19 .word (F3F(2,0x36,0x147)|RS1(a)|RS2(b)|RD(c));
31 .word (F3F(2, 0x19, 0)|RS1(a)|RS2(b)|RS3(c)|RD(d));
33 .word (F3F(2, 0x19, 1)|RS1(a)|RS2(b)|RS3(c)|RD(d));
35 .word (F3F(2, 0x19, 2)|RS1(a)|RS2(b)|RS3(c)|RD(d));
37 .word (F3F(2, 0x19, 3)|RS1(a)|RS2(b)|RS3(c)|RD(d));
39 .word (F3F(2, 0x19, 4)|RS1(a)|RS2(b)|RS3(c)|RD(d));
41 .word (F3F(2, 0x19, 5)|RS1(a)|RS2(b)|RS3(c)|RD(d));
43 .word (F3F(2, 0x19, 6)|RS1(a)|RS2(b)|RS3(c)|RD(d));
45 .word (F3F(2, 0x19, 7)|RS1(a)|RS2(b)|RS3(c)|RD(d));
[all …]
/Linux-v6.1/arch/sparc/net/
Dbpf_jit_comp_32.c26 #define RS1(X) ((X) << 14) macro
71 (F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG))
113 *prog++ = SUB | RS1(G0) | RS2(r_A) | RD(r_A); \
118 *prog++ = OR | RS1(G0) | RS2(FROM) | RD(TO); \
123 *prog++ = OR | RS1(G0) | RS2(G0) | RD(REG); \
140 *prog++ = OPCODE | RS1(r_A) | RS2(r_X) | RD(r_A); \
161 _insn |= RS1(r_A) | RD(r_A); \
175 *prog++ = OR | IMMED | RS1(G0) | S13(K) | RD(DEST); \
184 *prog++ = LDPTRI | RS1(BASE) | S13(_off) | RD(DEST); \
190 *prog++ = LD32I | RS1(BASE) | S13(_off) | RD(DEST); \
[all …]
Dbpf_jit_comp_64.c55 #define RS1(X) ((X) << 14) macro
139 (F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG))
263 emit(OR | RS1(G0) | RS2(from) | RD(to), ctx); in emit_reg_move()
284 emit(XOR | IMMED | RS1(reg) | S13(lbits) | RD(reg), ctx); in emit_set_const_sext()
290 emit(opcode | RS1(dst) | RS2(src) | RD(dst), ctx); in emit_alu()
295 emit(opcode | RS1(a) | RS2(b) | RD(c), ctx); in emit_alu3()
304 insn |= RS1(dst) | RD(dst); in emit_alu_K()
323 insn |= RS1(src) | RD(dst); in emit_alu3_K()
340 emit(OR | IMMED | RS1(G0) | S13(K) | RD(dest), ctx); in emit_loadimm32()
350 emit(OR | IMMED | RS1(G0) | S13(K) | RD(dest), ctx); in emit_loadimm()
[all …]
/Linux-v6.1/arch/riscv/kernel/probes/
Dsimulate-insn.c65 * offset[11:0] | rs1 | 010 | rd | opcode in simulate_jalr()
151 * | imm[12] | imm[10:5] | rs2 | rs1 | funct3 | imm[4:1] | imm[11] | opcode | in simulate_branch()
153 * imm[12|10:5] rs2 rs1 000 imm[4:1|11] 1100011 BEQ in simulate_branch()
154 * imm[12|10:5] rs2 rs1 001 imm[4:1|11] 1100011 BNE in simulate_branch()
155 * imm[12|10:5] rs2 rs1 100 imm[4:1|11] 1100011 BLT in simulate_branch()
156 * imm[12|10:5] rs2 rs1 101 imm[4:1|11] 1100011 BGE in simulate_branch()
157 * imm[12|10:5] rs2 rs1 110 imm[4:1|11] 1100011 BLTU in simulate_branch()
158 * imm[12|10:5] rs2 rs1 111 imm[4:1|11] 1100011 BGEU in simulate_branch()
/Linux-v6.1/arch/arm64/kernel/
Dsleep.S15 * @rs1: register containing affinity level 1 bit shift
25 *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 rs3, u64 mpidr, u64 mask) {
32 * dst = (aff0 >> rs0 | aff1 >> rs1 | aff2 >> rs2 | aff3 >> rs3);
34 * Input registers: rs0, rs1, rs2, rs3, mpidr, mask
39 .macro compute_mpidr_hash dst, rs0, rs1, rs2, rs3, mpidr, mask
44 lsr \mask ,\mask, \rs1
45 orr \dst, \dst, \mask // dst|=(aff1>>rs1)
/Linux-v6.1/arch/arm/kernel/
Dsleep.S16 * @rs1: register containing affinity level 1 bit shift
25 *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 mpidr, u32 mask) {
31 * dst = (aff0 >> rs0 | aff1 >> rs1 | aff2 >> rs2);
33 * Input registers: rs0, rs1, rs2, mpidr, mask
38 .macro compute_mpidr_hash dst, rs0, rs1, rs2, mpidr, mask
44 ARM( orr \dst, \dst, \mask, lsr \rs1 ) @ dst|=(aff1>>rs1)
45 THUMB( lsr \mask, \mask, \rs1 )
/Linux-v6.1/arch/arm/include/debug/
Dvexpress.S28 @ - all other (RS1 complaint) tiles use UART mapped
40 @ RS1 memory map
/Linux-v6.1/arch/mips/crypto/
Dpoly1305-mips.pl226 my ($h0,$h1,$h2,$r0,$r1,$rs1,$d0,$d1,$d2) =
283 ld $rs1,40($ctx)
380 dmultu ($rs1,$d1) # h1*5*r1
383 mflo ($tmp0,$rs1,$d1)
384 mfhi ($tmp1,$rs1,$d1)
399 dmultu ($rs1,$d2) # h2*5*r1
402 mflo ($tmp2,$rs1,$d2)
733 my ($h0,$h1,$h2,$h3,$h4, $r0,$r1,$r2,$r3, $rs1,$rs2,$rs3) =
787 lw $rs1,36($ctx)
927 maddu $rs1,$d3 # d3*s1
[all …]
/Linux-v6.1/arch/riscv/kvm/
Dvcpu_exit.c76 * 0110010 00011 rs1 100 rd 1110011 in kvm_riscv_vcpu_unpriv_read()
101 * 0110110 00000 rs1 100 rd 1110011 in kvm_riscv_vcpu_unpriv_read()
104 * 0110100 00000 rs1 100 rd 1110011 in kvm_riscv_vcpu_unpriv_read()
/Linux-v6.1/arch/sparc/math-emu/
Dmath_32.c279 /* r is rd, b is rs2 and a is rs1. The *u arg tells in do_one_mathemu()
284 argp rs1 = NULL, rs2 = NULL, rd = NULL; in do_one_mathemu() local
355 switch (type & 0x3) { /* is rs1 single, double or quad? */ in do_one_mathemu()
369 rs1 = (argp)&fregs[freg]; in do_one_mathemu()
371 case 7: FP_UNPACK_QP (QA, rs1); break; in do_one_mathemu()
372 case 6: FP_UNPACK_DP (DA, rs1); break; in do_one_mathemu()
373 case 5: FP_UNPACK_SP (SA, rs1); break; in do_one_mathemu()
Dmath_64.c173 /* ftt tells which ftt it may happen in, r is rd, b is rs2 and a is rs1. The *u arg tells in do_mathemu()
359 argp rs1 = NULL, rs2 = NULL, rd = NULL; in do_mathemu() local
380 case 1: rs1 = (argp)&f->regs[freg]; in do_mathemu()
383 rs1 = (argp)&zero; in do_mathemu()
387 case 7: FP_UNPACK_QP (QA, rs1); break; in do_mathemu()
388 case 6: FP_UNPACK_DP (DA, rs1); break; in do_mathemu()
389 case 5: FP_UNPACK_SP (SA, rs1); break; in do_mathemu()
/Linux-v6.1/arch/arm/boot/dts/
Dvexpress-v2m.dtsi14 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
18 * CHANGES TO vexpress-v2m-rs1.dtsi!
Dxenvm-4.2.dts80 arm,v2m-memory-map = "rs1";
/Linux-v6.1/arch/arm64/boot/dts/arm/
Dvexpress-v2f-1xv7-ca53x2.dts16 #include "vexpress-v2m-rs1.dtsi"
/Linux-v6.1/Documentation/devicetree/bindings/net/
Dsff,sfp.yaml66 GPIO phandle and a specifier of the Tx Signaling Rate Select (AKA RS1)
/Linux-v6.1/drivers/edac/
Dpnd2_edac.h224 u32 rs1 : 5; member
/Linux-v6.1/include/linux/rtc/
Dds1685.h154 #define RTC_CTRL_A_RS_MASK 0x0f /* RS3 + RS2 + RS1 + RS0 */
311 /* E32K RS3 RS2 RS1 RS0 */

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