55 #define RS1(X)		((X) << 14)  macro
139 	(F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG))
263 	emit(OR | RS1(G0) | RS2(from) | RD(to), ctx);  in emit_reg_move()
284 		emit(XOR | IMMED | RS1(reg) | S13(lbits) | RD(reg), ctx);  in emit_set_const_sext()
290 	emit(opcode | RS1(dst) | RS2(src) | RD(dst), ctx);  in emit_alu()
295 	emit(opcode | RS1(a) | RS2(b) | RD(c), ctx);  in emit_alu3()
304 	insn |= RS1(dst) | RD(dst);  in emit_alu_K()
323 	insn |= RS1(src) | RD(dst);  in emit_alu3_K()
340 		emit(OR | IMMED | RS1(G0) | S13(K) | RD(dest), ctx);  in emit_loadimm32()
350 		emit(OR | IMMED | RS1(G0) | S13(K) | RD(dest), ctx);  in emit_loadimm()
360 		emit(OR | IMMED | RS1(G0) | S13(K) | RD(dest), ctx);  in emit_loadimm_sext()
462 		emit(OR | IMMED | RS1(dest) | S13(low_imm) | RD(dest), ctx);  in sparc_emit_set_const64_quick2()
504 		emit(OR | IMMED | RS1(G0) | S13(the_const) | RD(dest), ctx);  in emit_loadimm64()
563 				emit(OR | IMMED | RS1(G0) | S13(fast_int) | RD(dest), ctx);  in emit_loadimm64()
575 		emit(XOR | IMMED | RS1(dest) | S13(low_bits) | RD(dest), ctx);  in emit_loadimm64()
613 	emit(OR | RS1(dest) | RS2(tmp) | RD(dest), ctx);  in emit_loadimm64()
632 	emit(cb_opc | WDISP10(off << 2) | RS1(dst) | RS2(src), ctx);  in emit_cbcond()
640 	emit(cb_opc | IMMED | WDISP10(off << 2) | RS1(dst) | S5(imm), ctx);  in emit_cbcondi()
644 #define emit_write_y(REG, CTX)	emit(WR_Y | IMMED | RS1(REG) | S13(0), CTX)
647 	emit(SUBCC | RS1(R1) | RS2(R2) | RD(G0), CTX)
650 	emit(SUBCC | IMMED | RS1(R1) | S13(IMM) | RD(G0), CTX)
653 	emit(ANDCC | RS1(R1) | RS2(R2) | RD(G0), CTX)
656 	emit(ANDCC | IMMED | RS1(R1) | S13(IMM) | RD(G0), CTX)
813 	emit(SAVE | IMMED | RS1(SP) | S13(-stack_needed) | RD(SP), ctx);  in build_prologue()
819 		emit(ST32 | IMMED | RS1(SP) | S13(off) | RD(G0), ctx);  in build_prologue()
826 		emit(ADD | IMMED | RS1(FP) | S13(STACK_BIAS) | RD(vfp), ctx);  in build_prologue()
844 	emit(JMPL | IMMED | RS1(I7) | S13(8) | RD(G0), ctx);  in build_epilogue()
847 	emit(RESTORE | RS1(bpf2sparc[BPF_REG_0]) | RS2(G0) | RD(O0), ctx);  in build_epilogue()
860 	emit(LD32 | IMMED | RS1(bpf_array) | S13(off) | RD(tmp), ctx);  in emit_tail_call()
867 	emit(LD32 | IMMED | RS1(SP) | S13(off) | RD(tmp), ctx);  in emit_tail_call()
875 	emit(ST32 | IMMED | RS1(SP) | S13(off) | RD(tmp), ctx);  in emit_tail_call()
880 	emit(LD64 | IMMED | RS1(tmp) | S13(off) | RD(tmp), ctx);  in emit_tail_call()
888 	emit(LD64 | IMMED | RS1(tmp) | S13(off) | RD(tmp), ctx);  in emit_tail_call()
891 	emit(JMPL | IMMED | RS1(tmp) | S13(off) | RD(G0), ctx);  in emit_tail_call()
998 		emit(SUB | RS1(0) | RS2(dst) | RD(dst), ctx);  in build_insn()
1057 			emit(ST64 | RS1(tmp) | RS2(G0) | RD(dst), ctx);  in build_insn()
1058 			emit(LD64A | ASI(ASI_PL) | RS1(tmp) | RS2(G0) | RD(dst), ctx);  in build_insn()
1127 			emit(div | IMMED | RS1(dst) | S13(imm) | RD(tmp), ctx);  in build_insn()
1128 			emit(MULX | IMMED | RS1(tmp) | S13(imm) | RD(tmp), ctx);  in build_insn()
1129 			emit(SUB | RS1(dst) | RS2(tmp) | RD(dst), ctx);  in build_insn()
1136 			emit(div | RS1(dst) | RS2(tmp1) | RD(tmp), ctx);  in build_insn()
1137 			emit(MULX | RS1(tmp) | RS2(tmp1) | RD(tmp), ctx);  in build_insn()
1138 			emit(SUB | RS1(dst) | RS2(tmp) | RD(dst), ctx);  in build_insn()
1285 		emit(opcode | RS1(src) | rs2 | RD(dst), ctx);  in build_insn()
1331 		emit(opcode | RS1(dst) | rs2 | RD(tmp2), ctx);  in build_insn()
1368 		emit(opcode | RS1(dst) | rs2 | RD(src), ctx);  in build_insn()
1393 		emit(LD32 | RS1(tmp) | RS2(G0) | RD(tmp2), ctx);  in build_insn()
1395 		emit(CAS | ASI(ASI_P) | RS1(tmp) | RS2(tmp2) | RD(tmp3), ctx);  in build_insn()
1421 		emit(LD64 | RS1(tmp) | RS2(G0) | RD(tmp2), ctx);  in build_insn()
1423 		emit(CASX | ASI(ASI_P) | RS1(tmp) | RS2(tmp2) | RD(tmp3), ctx);  in build_insn()