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/Linux-v6.1/Documentation/riscv/
Dpatch-acceptance.rst1 .. SPDX-License-Identifier: GPL-2.0
7 --------
8 The RISC-V instruction set architecture is developed in the open:
9 in-progress drafts are available for all to review and to experiment
11 during the development process - sometimes in ways that are
13 challenge for RISC-V Linux maintenance. Linux maintainers disapprove
14 of churn, and the Linux development process prefers well-reviewed and
16 principles to the RISC-V-related code that will be accepted for
20 -------------------------
23 "Frozen" or "Ratified" by the RISC-V Foundation. (Developers may, of
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Dvm-layout.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Virtual Memory Layout on RISC-V Linux
10 This document describes the virtual memory layout used by the RISC-V Linux
13 RISC-V Linux Kernel 32bit
16 RISC-V Linux Kernel SV32
17 ------------------------
21 RISC-V Linux Kernel 64bit
24 The RISC-V privileged architecture document states that the 64bit addresses
25 "must have bits 63–48 all equal to bit 47, or else a page-fault exception will
28 the RISC-V Linux Kernel resides.
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Dboot-image-header.rst2 Boot image header in RISC-V Linux
8 This document only describes the boot image header details for RISC-V Linux.
13 The following 64-byte header is present in decompressed Linux kernel image::
28 ARM64 header. Thus, both ARM64 & RISC-V header can be combined into one common
34 - This header can also be reused to support EFI stub for RISC-V in future. EFI
40 - version field indicate header version number
50 - The "magic" field is deprecated as of version 0.2. In a future
55 - In current header, the flags field has only one field.
61 - Image size is mandatory for boot loader to load kernel image. Booting will
/Linux-v6.1/Documentation/translations/it_IT/riscv/
Dpatch-acceptance.rst1 .. include:: ../disclaimer-ita.rst
3 :Original: :doc:`../../../riscv/patch-acceptance`
10 ------------
12 L'insieme di istruzioni RISC-V sono sviluppate in modo aperto: le
15 dei nuovi moduli o estensioni possono cambiare in fase di sviluppo - a
18 supporto RISC-V nel kernel Linux. I manutentori Linux non amano
22 relativo all'architettura RISC-V che verrà accettato per l'inclusione
26 -------------------------------------------------------------------------
29 RISC-V li classifica come "Frozen" o "Retified". (Ovviamente, gli
33 In aggiunta, la specifica RISC-V permette agli implementatori di
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/Linux-v6.1/Documentation/devicetree/bindings/riscv/
Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V bindings for 'cpus' DT nodes
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
29 - items:
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/Linux-v6.1/Documentation/devicetree/bindings/interrupt-controller/
Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
27 - compatible : "riscv,cpu-intc"
28 - #interrupt-cells : should be <1>. The interrupt sources are defined by the
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Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
21 Each interrupt can be enabled on per-context basis. Any context can claim
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/Linux-v6.1/drivers/cpuidle/
DKconfig.riscv1 # SPDX-License-Identifier: GPL-2.0-only
3 # RISC-V CPU Idle drivers
7 bool "RISC-V SBI CPU idle Driver"
13 Select this option to enable RISC-V SBI firmware based CPU idle
14 driver for RISC-V systems. This drivers also supports hierarchical
/Linux-v6.1/Documentation/translations/zh_CN/riscv/
Dvm-layout.rst1 .. SPDX-License-Identifier: GPL-2.0
2 .. include:: ../disclaimer-zh_CN.rst
4 :Original: Documentation/riscv/vm-layout.rst
12 RISC-V Linux上的虚拟内存布局
18 这份文件描述了RISC-V Linux内核使用的虚拟内存布局。
20 32位 RISC-V Linux 内核
23 RISC-V Linux Kernel SV32
24 ------------------------
28 64位 RISC-V Linux 内核
31 RISC-V特权架构文档指出，64位地址 "必须使第63-48位值都等于第47位，否则将发生缺页异常。"：这将虚
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Dpatch-acceptance.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/riscv/patch-acceptance.rst
11 .. _cn_riscv_patch-acceptance:
17 ----
18 RISC-V指令集体系结构是公开开发的：
20 生更改---有时以不兼容的方式对以前的草案进行更改。这种灵活性可能会给RISC-V Linux
22 们希望推广同样的规则到即将被内核合并的RISC-V相关代码。
25 ----------------
26 我们仅接受相关标准已经被RISC-V基金会标准为“已批准”或“已冻结”的扩展或模块的补丁。
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/Linux-v6.1/drivers/perf/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
45 tristate "Arm CMN-600 PMU support"
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
56 Say y if you want to use CPU performance monitors on ARM-based
61 bool "RISC-V PMU framework"
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Driscv_pmu_legacy.c1 // SPDX-License-Identifier: GPL-2.0
3 * RISC-V performance counter support.
7 * This implementation is based on old RISC-V perf and ARM perf event code
22 struct perf_event_attr *attr = &event->attr; in pmu_legacy_ctr_get_idx()
24 if (event->attr.type != PERF_TYPE_HARDWARE) in pmu_legacy_ctr_get_idx()
25 return -EOPNOTSUPP; in pmu_legacy_ctr_get_idx()
26 if (attr->config == PERF_COUNT_HW_CPU_CYCLES) in pmu_legacy_ctr_get_idx()
28 else if (attr->config == PERF_COUNT_HW_INSTRUCTIONS) in pmu_legacy_ctr_get_idx()
31 return -EOPNOTSUPP; in pmu_legacy_ctr_get_idx()
42 struct hw_perf_event *hwc = &event->hw; in pmu_legacy_read_ctr()
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/Linux-v6.1/drivers/media/pci/cx88/
Dcx88-alsa.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include "cx88-reg.h"
22 #include <linux/dma-mapping.h>
37 chip->core->name, ##arg); \
41 * Data type declarations - Can be moded to a header file later
46 struct cx88_riscmem risc; member
81 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
115 struct cx88_audio_buffer *buf = chip->buf; in _cx88_start_audio_dma()
116 struct cx88_core *core = chip->core; in _cx88_start_audio_dma()
119 /* Make sure RISC/FIFO are off before changing FIFO/RISC settings */ in _cx88_start_audio_dma()
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Dcx88-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * (c) 2005-2006 Mauro Carvalho Chehab <mchehab@kernel.org>
9 * - Multituner support
10 * - video_ioctl2 conversion
11 * - PAL/M fixes
29 #include <media/v4l2-common.h>
30 #include <media/v4l2-ioctl.h>
36 /* ------------------------------------------------------------------ */
64 #define NO_SYNC_LINE (-1U)
91 offset -= sg_dma_len(sg); in cx88_risc_field()
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/Linux-v6.1/drivers/media/pci/cx23885/
Dcx23885-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
24 #include "altera-ci.h"
25 #include "cx23888-ir.h"
26 #include "cx23885-ir.h"
27 #include "cx23885-av.h"
28 #include "cx23885-input.h"
38 * encountered is "mpeg risc op code error". Only Ryzen platforms employ
45 …PARM_DESC(dma_reset_workaround, "periodic RiSC dma engine reset; 0-force disable, 1-driver detect …
51 static unsigned int card[] = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
63 #define NO_SYNC_LINE (-1U)
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/Linux-v6.1/drivers/clocksource/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
60 bool "OMAP dual-mode timer driver" if ARCH_K3 || COMPILE_TEST
64 Enables the support for the TI dual-mode timer driver.
180 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
203 32-bit free running decrementing counters.
238 bool "Integrator-AP timer driver" if COMPILE_TEST
241 Enables support for the Integrator-AP timer.
266 available on many OMAP-like platforms.
285 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
289 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
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/Linux-v6.1/tools/arch/riscv/include/uapi/asm/
Dunistd.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
23 #include <asm-generic/unistd.h>
26 * Allows the instruction cache to be flushed from userspace. Despite RISC-V
31 * thread->hart mappings), so we've defined a RISC-V specific system call to
/Linux-v6.1/arch/riscv/include/uapi/asm/
Dunistd.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
26 #include <asm-generic/unistd.h>
29 * Allows the instruction cache to be flushed from userspace. Despite RISC-V
34 * thread->hart mappings), so we've defined a RISC-V specific system call to
/Linux-v6.1/arch/riscv/kernel/
Dcpu.c1 // SPDX-License-Identifier: GPL-2.0-only
17 * Returns the hart ID of the given device tree node, or -ENODEV if the node
18 * isn't an enabled and valid RISC-V hart node.
26 return -ENODEV; in riscv_of_processor_hartid()
32 return -ENODEV; in riscv_of_processor_hartid()
37 return -ENODEV; in riscv_of_processor_hartid()
42 return -ENODEV; in riscv_of_processor_hartid()
44 if (isa[0] != 'r' || isa[1] != 'v') { in riscv_of_processor_hartid()
46 return -ENODEV; in riscv_of_processor_hartid()
56 * RISC-V core (HART) node and extract the cpuid from it.
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Dsys_riscv.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <asm-generic/mman-common.h>
19 return -EINVAL; in riscv_sys_mmap()
22 offset >> (PAGE_SHIFT - page_shift_offset)); in riscv_sys_mmap()
48 * Allows the instruction cache to be flushed from userspace. Despite RISC-V
53 * thread->hart mappings), so we've defined a RISC-V specific system call to
66 return -EINVAL; in SYSCALL_DEFINE3()
68 flush_icache_mm(current->mm, flags & SYS_RISCV_FLUSH_ICACHE_LOCAL); in SYSCALL_DEFINE3()
/Linux-v6.1/Documentation/devicetree/bindings/timer/
Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
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/Linux-v6.1/Documentation/devicetree/bindings/cpu/
Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
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/Linux-v6.1/arch/riscv/include/asm/
Dhwcap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
29 #define RISCV_ISA_EXT_a ('a' - 'a')
30 #define RISCV_ISA_EXT_c ('c' - 'a')
31 #define RISCV_ISA_EXT_d ('d' - 'a')
32 #define RISCV_ISA_EXT_f ('f' - 'a')
33 #define RISCV_ISA_EXT_h ('h' - 'a')
34 #define RISCV_ISA_EXT_i ('i' - 'a')
35 #define RISCV_ISA_EXT_m ('m' - 'a')
36 #define RISCV_ISA_EXT_s ('s' - 'a')
37 #define RISCV_ISA_EXT_u ('u' - 'a')
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/Linux-v6.1/include/uapi/linux/
Delf-em.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
14 #define EM_MIPS 8 /* MIPS R3000 (officially, big-endian only) */
18 #define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian */
19 #define EM_MIPS_RS4_BE 10 /* MIPS R4000 big-endian */
28 #define EM_SPARCV9 43 /* SPARC v9 64-bit */
30 #define EM_IA_64 50 /* HP/Intel IA-64 */
31 #define EM_X86_64 62 /* AMD x86-64 */
33 #define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */
36 #define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */
40 #define EM_UNICORE 110 /* UniCore-32 */
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/Linux-v6.1/drivers/firmware/efi/libstub/
Driscv-stub.c1 // SPDX-License-Identifier: GPL-2.0
16 * RISC-V requires the kernel image to placed 2 MB aligned base for 64 bit and
37 return -EINVAL; in get_boot_hartid_from_fdt()
41 return -EINVAL; in get_boot_hartid_from_fdt()
43 prop = fdt_getprop((void *)fdt, chosen_node, "boot-hartid", &len); in get_boot_hartid_from_fdt()
45 return -EINVAL; in get_boot_hartid_from_fdt()
52 return -EINVAL; in get_boot_hartid_from_fdt()
89 unsigned long stext_offset = _start_kernel - _start; in efi_enter_kernel()
114 kernel_size = _edata - _start; in handle_kernel_image()
116 *image_size = kernel_size + (_end - _edata); in handle_kernel_image()
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