1 // SPDX-License-Identifier: GPL-2.0
3  * RISC-V performance counter support.
7  * This implementation is based on old RISC-V perf and ARM perf event code
22 	struct perf_event_attr *attr = &event->attr;  in pmu_legacy_ctr_get_idx()
24 	if (event->attr.type != PERF_TYPE_HARDWARE)  in pmu_legacy_ctr_get_idx()
25 		return -EOPNOTSUPP;  in pmu_legacy_ctr_get_idx()
26 	if (attr->config == PERF_COUNT_HW_CPU_CYCLES)  in pmu_legacy_ctr_get_idx()
28 	else if (attr->config == PERF_COUNT_HW_INSTRUCTIONS)  in pmu_legacy_ctr_get_idx()
31 		return -EOPNOTSUPP;  in pmu_legacy_ctr_get_idx()
42 	struct hw_perf_event *hwc = &event->hw;  in pmu_legacy_read_ctr()
43 	int idx = hwc->idx;  in pmu_legacy_read_ctr()
62 	struct hw_perf_event *hwc = &event->hw;  in pmu_legacy_ctr_start()
71 	local64_set(&hwc->prev_count, initial_val);  in pmu_legacy_ctr_start()
76  * compatible with new RISC-V PMU driver framework.
85 	pmu->cmask = BIT(RISCV_PMU_LEGACY_CYCLE) |  in pmu_legacy_init()
87 	pmu->ctr_start = pmu_legacy_ctr_start;  in pmu_legacy_init()
88 	pmu->ctr_stop = NULL;  in pmu_legacy_init()
89 	pmu->event_map = pmu_legacy_event_map;  in pmu_legacy_init()
90 	pmu->ctr_get_idx = pmu_legacy_ctr_get_idx;  in pmu_legacy_init()
91 	pmu->ctr_get_width = NULL;  in pmu_legacy_init()
92 	pmu->ctr_clear_idx = NULL;  in pmu_legacy_init()
93 	pmu->ctr_read = pmu_legacy_read_ctr;  in pmu_legacy_init()
95 	perf_pmu_register(&pmu->pmu, "cpu", PERF_TYPE_RAW);  in pmu_legacy_init()
104 		return -ENOMEM;  in pmu_legacy_device_probe()
129 	pdev = platform_device_register_simple(RISCV_PMU_LEGACY_PDEV_NAME, -1, NULL, 0);  in riscv_pmu_legacy_devinit()