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/Linux-v5.4/Documentation/devicetree/bindings/reset/
Dzynq-reset.txt1 Xilinx Zynq Reset Manager
8 - compatible: "xlnx,zynq-reset"
12 - #reset-cells: Must be 1
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
18 compatible = "xlnx,zynq-reset";
20 #reset-cells = <1>;
24 Reset outputs:
25 0 : soft reset
26 32 : ddr reset
27 64 : topsw reset
[all …]
Duniphier-reset.txt1 UniPhier reset controller
4 System reset
9 "socionext,uniphier-ld4-reset" - for LD4 SoC
10 "socionext,uniphier-pro4-reset" - for Pro4 SoC
11 "socionext,uniphier-sld8-reset" - for sLD8 SoC
12 "socionext,uniphier-pro5-reset" - for Pro5 SoC
13 "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC
14 "socionext,uniphier-ld11-reset" - for LD11 SoC
15 "socionext,uniphier-ld20-reset" - for LD20 SoC
16 "socionext,uniphier-pxs3-reset" - for PXs3 SoC
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Dreset.txt1 = Reset Signal Device Tree Bindings =
3 This binding is intended to represent the hardware reset signals present
4 internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
8 Hardware blocks typically receive a reset signal. This signal is generated by
9 a reset provider (e.g. power management or clock module) and received by a
10 reset consumer (the module being reset, or a module managing when a sub-
11 ordinate module is reset). This binding exists to represent the provider and
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
16 provider. The length (number of cells) and semantics of the reset specifier
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Dti-syscon-reset.txt1 TI SysCon Reset Controller
4 Almost all SoCs have hardware modules that require reset control in addition
5 to clock and power control for their functionality. The reset control is
12 A SysCon Reset Controller node defines a device that uses a syscon node
13 and provides reset management functionality for various hardware modules
16 SysCon Reset Controller Node
18 Each of the reset provider/controller nodes should be a child of a syscon
27 "ti,syscon-reset"
28 - #reset-cells : Should be 1. Please see the reset consumer node below
30 - ti,reset-bits : Contains the reset control register information
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Dsnps,hsdk-reset.txt1 Binding for the Synopsys HSDK reset controller
3 This binding uses the common reset binding[1].
5 [1] Documentation/devicetree/bindings/reset/reset.txt
8 - compatible: should be "snps,hsdk-reset".
9 - reg: should always contain 2 pairs address - length: first for reset
10 configuration register and second for corresponding SW reset and status bits
12 - #reset-cells: from common reset binding; Should always be set to 1.
15 reset: reset@880 {
16 compatible = "snps,hsdk-reset";
17 #reset-cells = <1>;
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Dfsl,imx7-src.txt1 Freescale i.MX7 System Reset Controller
4 Please also refer to reset.txt in this directory for common reset
15 - #reset-cells: 1, see below
19 src: reset-controller@30390000 {
23 #reset-cells = <1>;
27 Specifying reset lines connected to IP modules
30 The system reset controller can be used to reset various set of
31 peripherals. Device nodes that need access to reset lines should
32 specify them as a reset phandle in their corresponding node as
33 specified in reset.txt.
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Dimg,pistachio-reset.txt1 Pistachio Reset Controller
4 This binding describes a reset controller device that is used to enable and
5 disable individual IP blocks within the Pistachio SoC using "soft reset"
8 The actual action taken when soft reset is asserted is hardware dependent.
13 Please refer to Documentation/devicetree/bindings/reset/reset.txt
14 for common reset controller binding usage.
18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
31 pistachio_reset: reset-controller {
32 compatible = "img,pistachio-reset";
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Dsnps,axs10x-reset.txt1 Binding for the AXS10x reset controller
4 to control reset signals of selected peripherals. For example DW GMAC, etc...
6 represents up-to 32 reset lines.
11 This binding uses the common reset binding[1].
13 [1] Documentation/devicetree/bindings/reset/reset.txt
16 - compatible: should be "snps,axs10x-reset".
17 - reg: should always contain pair address - length: for creg reset
19 - #reset-cells: from common reset binding; Should always be set to 1.
22 reset: reset-controller@11220 {
23 compatible = "snps,axs10x-reset";
[all …]
Dti,sci-reset.txt1 Texas Instruments System Control Interface (TI-SCI) Reset Controller
12 TI-SCI Reset Controller Node
14 This reset controller node uses the TI SCI protocol to perform the reset
20 - compatible : Should be "ti,sci-reset"
21 - #reset-cells : Should be 2. Please see the reset consumer node below for
24 TI-SCI Reset Consumer Nodes
26 Each of the reset consumer nodes should have the following properties,
31 - resets : A phandle and reset specifier pair, one pair for each reset
33 The phandle should point to the TI-SCI reset controller node,
34 and the reset specifier should have 2 cell-values. The first
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/Linux-v5.4/drivers/reset/
DKconfig6 bool "Reset Controller Support"
9 Generic Reset Controller support.
11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
22 This option enables support for the external reset functions for
26 bool "AR71xx Reset Driver" if COMPILE_TEST
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
33 bool "AXS10x Reset Driver" if COMPILE_TEST
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Dreset-ti-sci.c2 * Texas Instrument's System Control Interface (TI-SCI) reset driver
22 #include <linux/reset-controller.h>
26 * struct ti_sci_reset_control - reset control structure
28 * @reset_mask: reset mask to use for toggling reset
38 * struct ti_sci_reset_data - reset controller information structure
39 * @rcdev: reset controller entity
40 * @dev: reset controller device pointer
42 * @idr: idr structure for mapping ids to reset control structures
55 * ti_sci_reset_set() - program a device's reset
56 * @rcdev: reset controller entity
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DMakefile6 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
7 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
8 obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
9 obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
10 obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
11 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
12 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
13 obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
14 obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
15 obj-$(CONFIG_RESET_MESON) += reset-meson.o
[all …]
Dreset-ti-syscon.c2 * TI SYSCON regmap reset driver
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/reset/ti-syscon.h>
28 * struct ti_syscon_reset_control - reset control structure
29 * @assert_offset: reset assert control register offset from syscon base
30 * @assert_bit: reset assert bit in the reset assert control register
31 * @deassert_offset: reset deassert control register offset from syscon base
32 * @deassert_bit: reset deassert bit in the reset deassert control register
33 * @status_offset: reset status register offset from syscon base
34 * @status_bit: reset status bit in the reset status register
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Dcore.c3 * Reset Controller framework
15 #include <linux/reset.h>
16 #include <linux/reset-controller.h>
26 * struct reset_control - a reset control
27 * @rcdev: a pointer to the reset controller device
28 * this reset control belongs to
29 * @list: list entry for the rcdev's reset controller list
30 * @id: ID of the reset controller in the reset
35 * @deassert_cnt: Number of times this reset line has been deasserted
36 * @triggered_count: Number of times this reset line has been reset. Currently
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Dreset-scmi.c3 * ARM System Control and Management Interface (ARM SCMI) reset driver
11 #include <linux/reset-controller.h>
15 * struct scmi_reset_data - reset controller information structure
16 * @rcdev: reset controller entity
28 * scmi_reset_assert() - assert device reset
29 * @rcdev: reset controller entity
30 * @id: ID of the reset to be asserted
32 * This function implements the reset driver op to assert a device's reset
46 * scmi_reset_deassert() - deassert device reset
47 * @rcdev: reset controller entity
[all …]
/Linux-v5.4/drivers/infiniband/hw/i40iw/
Di40iw_register.h38 #define I40E_GLGEN_STAT 0x000B612C /* Reset: POR */
40 #define I40E_PFHMC_PDINV 0x000C0300 /* Reset: PFR */
54 #define I40E_PFINT_DYN_CTLN(_INTPF) (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
62 …FINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */
63 #define I40E_GLHMC_VFPDINV(_i) (0x000C8300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CO…
67 #define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */
70 #define I40E_GLPCI_DREVID 0x0009C480 /* Reset: PCIR */
74 #define I40E_PFPE_AEQALLOC 0x00131180 /* Reset: PFR */
77 #define I40E_PFPE_CCQPHIGH 0x00008200 /* Reset: PFR */
80 #define I40E_PFPE_CCQPLOW 0x00008180 /* Reset: PFR */
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/Linux-v5.4/Documentation/devicetree/bindings/power/reset/
Dkeystone-reset.txt1 * Device tree bindings for Texas Instruments keystone reset
3 This node is intended to allow SoC reset in case of software reset
6 The Keystone SoCs can contain up to 4 watchdog timers to reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
8 block. The Reset Mux block can be configured to cause reset or not.
10 Additionally soft or hard reset can be configured.
14 - compatible: ti,keystone-reset
18 reset control registers.
26 - ti,soft-reset: Boolean option indicating soft reset.
27 By default hard reset is used.
[all …]
/Linux-v5.4/drivers/net/ethernet/intel/i40e/
Di40e_register.h7 #define I40E_GL_ARQBAH 0x000801C0 /* Reset: EMPR */
10 #define I40E_GL_ARQBAL 0x000800C0 /* Reset: EMPR */
13 #define I40E_GL_ARQH 0x000803C0 /* Reset: EMPR */
16 #define I40E_GL_ARQT 0x000804C0 /* Reset: EMPR */
19 #define I40E_GL_ATQBAH 0x00080140 /* Reset: EMPR */
22 #define I40E_GL_ATQBAL 0x00080040 /* Reset: EMPR */
25 #define I40E_GL_ATQH 0x00080340 /* Reset: EMPR */
28 #define I40E_GL_ATQLEN 0x00080240 /* Reset: EMPR */
39 #define I40E_GL_ATQT 0x00080440 /* Reset: EMPR */
42 #define I40E_PF_ARQBAH 0x00080180 /* Reset: EMPR */
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/Linux-v5.4/include/linux/
Dreset.h138 * to a reset controller.
139 * @dev: device to be reset by the controller
140 * @id: reset line name
147 * reset-controls.
159 * exclusive reference to a reset
161 * @dev: device to be reset by the controller
162 * @id: reset line name
165 * reset-controls returned by this function must be acquired via
180 * reset controller.
181 * @dev: device to be reset by the controller
[all …]
Dreset-controller.h10 * struct reset_control_ops - reset controller driver callbacks
12 * @reset: for self-deasserting resets, does all necessary
13 * things to reset the device
14 * @assert: manually assert the reset line, if supported
15 * @deassert: manually deassert the reset line, if supported
16 * @status: return the status of the reset line, if supported
19 int (*reset)(struct reset_controller_dev *rcdev, unsigned long id); member
32 * @list: internal list of all reset lookup entries
33 * @provider: name of the reset controller device controlling this reset line
34 * @index: ID of the reset controller in the reset controller device
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/Linux-v5.4/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra20-host1x.txt18 - resets: Must contain an entry for each entry in reset-names.
19 See ../reset/reset.txt for details.
20 - reset-names: Must include the following entries:
34 - resets: Must contain an entry for each entry in reset-names.
35 See ../reset/reset.txt for details.
36 - reset-names: Must include the following entries:
47 - resets: Must contain an entry for each entry in reset-names.
48 See ../reset/reset.txt for details.
49 - reset-names: Must include the following entries:
60 - resets: Must contain an entry for each entry in reset-names.
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/pci/
Dqcom,pcie.txt132 Definition: List of phandle and reset specifier pairs as listed
133 in reset-names property
135 - reset-names:
139 - "axi" AXI reset
140 - "ahb" AHB reset
141 - "por" POR reset
142 - "pci" PCI reset
143 - "phy" PHY reset
145 - reset-names:
149 - "core" Core reset
[all …]
/Linux-v5.4/drivers/net/ethernet/ibm/emac/
Demac.h30 u32 mr1; /* Reset */
33 u32 rmr; /* Reset */
35 u32 iser; /* Reset */
36 u32 iahr; /* Reset, R, T */
37 u32 ialr; /* Reset, R, T */
38 u32 vtpid; /* Reset, R, T */
39 u32 vtci; /* Reset, R, T */
40 u32 ptr; /* Reset, T */
44 u32 iaht1; /* Reset, R */
45 u32 iaht2; /* Reset, R */
[all …]
/Linux-v5.4/drivers/gpu/drm/i915/gt/
Dintel_reset.c86 /* Cool contexts are too cool to be banned! (Used for reset testing.) */ in context_mark_guilty()
152 /* Assert reset for at least 20 usec, and wait for acknowledgement. */ in i915_do_reset()
157 /* Clear the reset request. */ in i915_do_reset()
200 DRM_DEBUG_DRIVER("Wait for media reset failed\n"); in g4x_do_reset()
208 DRM_DEBUG_DRIVER("Wait for render reset failed\n"); in g4x_do_reset()
235 DRM_DEBUG_DRIVER("Wait for render reset failed\n"); in ironlake_do_reset()
246 DRM_DEBUG_DRIVER("Wait for media reset failed\n"); in ironlake_do_reset()
256 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
269 /* Wait for the device to ack the reset requests */ in gen6_hw_domain_reset()
275 DRM_DEBUG_DRIVER("Wait for 0x%08x engines reset failed\n", in gen6_hw_domain_reset()
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/Linux-v5.4/drivers/net/ethernet/intel/iavf/
Diavf_register.h7 #define IAVF_VF_ARQBAH1 0x00006000 /* Reset: EMPR */
8 #define IAVF_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */
9 #define IAVF_VF_ARQH1 0x00007400 /* Reset: EMPR */
12 #define IAVF_VF_ARQLEN1 0x00008000 /* Reset: EMPR */
21 #define IAVF_VF_ARQT1 0x00007000 /* Reset: EMPR */
22 #define IAVF_VF_ATQBAH1 0x00007800 /* Reset: EMPR */
23 #define IAVF_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */
24 #define IAVF_VF_ATQH1 0x00006400 /* Reset: EMPR */
25 #define IAVF_VF_ATQLEN1 0x00006800 /* Reset: EMPR */
34 #define IAVF_VF_ATQT1 0x00008400 /* Reset: EMPR */
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