Home
last modified time | relevance | path

Searched full:otp (Results 1 – 25 of 173) sorted by relevance

1234567

/Linux-v5.10/drivers/nvmem/
Drockchip-otp.c3 * Rockchip OTP Driver
22 /* OTP Register Offsets */
35 /* OTP Register bits and masks */
67 "otp", "apb_pclk", "phy",
74 static int rockchip_otp_reset(struct rockchip_otp *otp) in rockchip_otp_reset() argument
78 ret = reset_control_assert(otp->rst); in rockchip_otp_reset()
80 dev_err(otp->dev, "failed to assert otp phy %d\n", ret); in rockchip_otp_reset()
86 ret = reset_control_deassert(otp->rst); in rockchip_otp_reset()
88 dev_err(otp->dev, "failed to deassert otp phy %d\n", ret); in rockchip_otp_reset()
95 static int rockchip_otp_wait_status(struct rockchip_otp *otp, u32 flag) in rockchip_otp_wait_status() argument
[all …]
Dmxs-ocotp.c3 * Freescale MXS On-Chip OTP driver
36 static int mxs_ocotp_wait(struct mxs_ocotp *otp) in mxs_ocotp_wait() argument
42 status = readl(otp->base); in mxs_ocotp_wait()
61 struct mxs_ocotp *otp = context; in mxs_ocotp_read() local
65 ret = clk_enable(otp->clk); in mxs_ocotp_read()
69 writel(BM_OCOTP_CTRL_ERROR, otp->base + STMP_OFFSET_REG_CLR); in mxs_ocotp_read()
71 ret = mxs_ocotp_wait(otp); in mxs_ocotp_read()
76 writel(BM_OCOTP_CTRL_RD_BANK_OPEN, otp->base + STMP_OFFSET_REG_SET); in mxs_ocotp_read()
81 ret = mxs_ocotp_wait(otp); in mxs_ocotp_read()
90 *buf++ = readl(otp->base + offset); in mxs_ocotp_read()
[all …]
Dlpc18xx_otp.c3 * NXP LPC18xx/43xx OTP memory NVMEM driver
10 * TODO: add support for writing OTP register via API in boot ROM.
22 * LPC18xx OTP memory contains 4 banks with 4 32-bit words. Bank 0 starts
44 struct lpc18xx_otp *otp = context; in lpc18xx_otp_read() local
54 *buf++ = readl(otp->base + i * LPC18XX_OTP_WORD_SIZE); in lpc18xx_otp_read()
60 .name = "lpc18xx-otp",
70 struct lpc18xx_otp *otp; in lpc18xx_otp_probe() local
73 otp = devm_kzalloc(&pdev->dev, sizeof(*otp), GFP_KERNEL); in lpc18xx_otp_probe()
74 if (!otp) in lpc18xx_otp_probe()
78 otp->base = devm_ioremap_resource(&pdev->dev, res); in lpc18xx_otp_probe()
[all …]
DKconfig36 tristate "i.MX 6/7/8 On-Chip OTP Controller support"
40 This is a driver for the On-Chip OTP Controller (OCOTP) available on
48 tristate "i.MX8 SCU On-Chip OTP Controller support"
52 This is a driver for the SCU On-Chip OTP Controller (OCOTP)
78 tristate "NXP LPC18XX OTP Memory Support"
82 Say Y here to include support for NXP LPC18xx OTP memory found on
88 tristate "Freescale MXS On-Chip OTP Memory Support"
141 tristate "Rockchip OTP controller support"
146 from otp, such as cpu-leakage.
152 tristate "Broadcom On-Chip OTP Controller support"
[all …]
Dimx-ocotp.c27 * OTP Bank0 Word0
30 * of two consecutive OTP words.
215 * ipg_clk. OTP writes will work at maximum bus frequencies as long in imx_ocotp_set_imx6_timing()
218 * Note: there are minimum timings required to ensure an OTP fuse burns in imx_ocotp_set_imx6_timing()
227 * - Minimum STROBE_READ i.e. the time to wait post OTP fuse burn before in imx_ocotp_set_imx6_timing()
237 * value will mess up a re-load of the shadow registers post OTP in imx_ocotp_set_imx6_timing()
290 /* allow only writing one complete OTP word at a time */ in imx_ocotp_write()
328 * In banked/i.MX7 mode the OTP register bank goes into waddr in imx_ocotp_write()
338 * OTP write/read address specifies one of 128 word address in imx_ocotp_write()
354 * protect programming same OTP bit twice, before program OCOTP will in imx_ocotp_write()
[all …]
Dstm32-romem.c50 static int stm32_bsec_smc(u8 op, u32 otp, u32 data, u32 *result) in stm32_bsec_smc() argument
55 arm_smccc_smc(STM32_SMC_BSEC, op, otp, data, 0, 0, 0, 0, &res); in stm32_bsec_smc()
86 u32 otp = i >> 2; in stm32_bsec_read() local
88 if (otp < STM32MP15_BSEC_NUM_LOWER) { in stm32_bsec_read()
93 ret = stm32_bsec_smc(STM32_SMC_READ_SHADOW, otp, 0, in stm32_bsec_read()
96 dev_err(dev, "Can't read data%d (%d)\n", otp, in stm32_bsec_read()
182 { .compatible = "st,stm32f4-otp", }, {
DMakefile34 obj-$(CONFIG_ROCKCHIP_OTP) += nvmem-rockchip-otp.o
35 nvmem-rockchip-otp-y := rockchip-otp.o
/Linux-v5.10/drivers/mfd/
Dab3100-otp.c6 * Driver to read out OTP from the AB3100 Mixed-signal circuit
19 /* The OTP registers */
33 * @locked: whether the OTP is locked, after locking, no more bits
36 * @freq: clocking frequency for the OTP, this frequency is either
62 static int __init ab3100_otp_read(struct ab3100_otp *otp) in ab3100_otp_read() argument
68 err = abx500_get_register_interruptible(otp->dev, 0, in ab3100_otp_read()
71 dev_err(otp->dev, "unable to read OTPP register\n"); in ab3100_otp_read()
75 err = abx500_get_register_page_interruptible(otp->dev, 0, in ab3100_otp_read()
78 dev_err(otp->dev, "unable to read OTP register page\n"); in ab3100_otp_read()
82 /* Cache OTP properties, they never change by nature */ in ab3100_otp_read()
[all …]
Dwm831x-otp.c3 * wm831x-otp.c -- OTP for Wolfson WM831x PMICs
19 #include <linux/mfd/wm831x/otp.h>
/Linux-v5.10/Documentation/devicetree/bindings/nvmem/
Drockchip-otp.txt1 Rockchip internal OTP (One Time Programmable) memory device tree bindings
5 - "rockchip,px30-otp" - for PX30 SoCs.
6 - "rockchip,rk3308-otp" - for RK3308 SoCs.
9 - clock-names: Should be "otp", "apb_pclk" and "phy".
17 otp: otp@ff290000 {
18 compatible = "rockchip,px30-otp";
24 clock-names = "otp", "apb_pclk", "phy";
Dlpc1850-otp.txt1 * NXP LPC18xx OTP memory
3 Internal OTP (One Time Programmable) memory for NXP LPC18xx/43xx devices.
6 - compatible: Should be "nxp,lpc1850-otp"
15 otp: otp@40045000 {
16 compatible = "nxp,lpc1850-otp";
Dst,stm32-romem.yaml11 flash, OTP, read-only HW regs... This contains various information such as:
24 - st,stm32f4-otp
32 st,non-secure-otp:
50 compatible = "st,stm32f4-otp";
61 st,non-secure-otp;
Dbrcm,ocotp.txt1 Broadcom OTP memory controller
8 - reg: Base address of the OTP controller.
13 otp: otp@301c800 {
/Linux-v5.10/drivers/net/wireless/intel/iwlwifi/
Diwl-eeprom-read.c143 IWL_ERR(trans, "OTP with bad signature: 0x%08x\n", gp); in iwl_eeprom_verify_signature()
150 "bad EEPROM/OTP signature, type=%s, EEPROM_GP=0x%08x\n", in iwl_eeprom_verify_signature()
151 nvm_is_otp ? "OTP" : "EEPROM", gp); in iwl_eeprom_verify_signature()
158 * OTP related functions
174 /* OTP only valid for CP/PP and after */ in iwl_nvm_is_otp()
208 * this is only applicable for HW with OTP shadow RAM in iwl_init_otp_access()
231 IWL_ERR(trans, "Time out reading OTP[%d]\n", addr); in iwl_read_otp_word()
239 /* set the uncorrectable OTP ECC bit for acknowledgment */ in iwl_read_otp_word()
242 IWL_ERR(trans, "Uncorrectable OTP ECC error, abort OTP read\n"); in iwl_read_otp_word()
247 /* set the correctable OTP ECC bit for acknowledgment */ in iwl_read_otp_word()
[all …]
Diwl-agn-hw.h104 #define OTP_MAX_LL_ITEMS_1000 (3) /* OTP blocks for 1000 */
105 #define OTP_MAX_LL_ITEMS_6x00 (4) /* OTP blocks for 6x00 */
106 #define OTP_MAX_LL_ITEMS_6x50 (7) /* OTP blocks for 6x50 */
107 #define OTP_MAX_LL_ITEMS_2x00 (4) /* OTP blocks for 2x00 */
/Linux-v5.10/drivers/net/wireless/mediatek/mt76/mt7615/
Deeprom.c54 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, len, GFP_KERNEL); in mt7615_efuse_init()
55 dev->mt76.otp.size = len; in mt7615_efuse_init()
56 if (!dev->mt76.otp.data) in mt7615_efuse_init()
59 buf = dev->mt76.otp.data; in mt7615_efuse_init()
272 u8 *otp = dev->mt76.otp.data; in mt7615_apply_cal_free_data() local
275 if (!otp) in mt7615_apply_cal_free_data()
279 if (!otp[ical[i]]) in mt7615_apply_cal_free_data()
283 eeprom[ical[i]] = otp[ical[i]]; in mt7615_apply_cal_free_data()
286 eeprom[ical_nocheck[i]] = otp[ical_nocheck[i]]; in mt7615_apply_cal_free_data()
295 u8 *otp = dev->mt76.otp.data; in mt7622_apply_cal_free_data() local
[all …]
/Linux-v5.10/drivers/net/wireless/mediatek/mt76/mt7603/
Deeprom.c51 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, len, GFP_KERNEL); in mt7603_efuse_init()
52 dev->mt76.otp.size = len; in mt7603_efuse_init()
53 if (!dev->mt76.otp.data) in mt7603_efuse_init()
56 buf = dev->mt76.otp.data; in mt7603_efuse_init()
109 if (!np || !of_property_read_bool(np, "mediatek,eeprom-merge-otp")) in mt7603_apply_cal_free_data()
164 if (dev->mt76.otp.data) { in mt7603_eeprom_init()
166 mt7603_apply_cal_free_data(dev, dev->mt76.otp.data); in mt7603_eeprom_init()
168 memcpy(dev->mt76.eeprom.data, dev->mt76.otp.data, in mt7603_eeprom_init()
/Linux-v5.10/include/linux/mfd/wm831x/
Dotp.h3 * include/linux/mfd/wm831x/otp.h -- OTP interface for WM831x
73 * R30728 (0x7808) - Factory OTP ID
84 * R30729 (0x7809) - Factory OTP 1
97 * R30730 (0x780A) - Factory OTP 2
104 * R30731 (0x780B) - Factory OTP 3
117 * R30732 (0x780C) - Factory OTP 4
128 * R30733 (0x780D) - Factory OTP 5
135 * R30736 (0x7810) - Customer OTP ID
/Linux-v5.10/drivers/mtd/nand/onenand/
DKconfig43 bool "OneNAND OTP Support"
47 Also, 1st Block of NAND Flash Array can be used as OTP.
49 The OTP block can be read, programmed and locked using the same
51 OTP block cannot be erased.
53 OTP block is fully-guaranteed to be a valid block.
Donenand_base.c15 * OTP support
50 /* Default OneNAND/Flex-OneNAND OTP options*/
51 static int otp; variable
53 module_param(otp, int, 0400);
54 MODULE_PARM_DESC(otp, "Corresponding behaviour of OneNAND in OTP"
55 "Syntax : otp=LOCK_TYPE"
56 "LOCK_TYPE : Keys issued, for specific OTP Lock type"
58 " : 1 -> OTP Block lock"
60 " : 3 -> BOTH OTP Block and 1st Block lock");
1897 /* Exclude 1st OTP and OTP blocks for cache program feature */ in onenand_write_ops_nolock()
[all …]
/Linux-v5.10/include/uapi/mtd/
Dmtd-abi.h123 /* OTP mode selection */
180 /* Set OTP (One-Time Programmable) mode (factory vs. user) */
182 /* Get number of OTP (One-Time Programmable) regions */
184 /* Get all OTP (One-Time Programmable) info about MTD */
260 * @MTD_FILE_MODE_NORMAL: OTP disabled, ECC enabled
261 * @MTD_FILE_MODE_OTP_FACTORY: OTP enabled in factory mode
262 * @MTD_FILE_MODE_OTP_USER: OTP enabled in user mode
263 * @MTD_FILE_MODE_RAW: OTP disabled, ECC disabled
/Linux-v5.10/Documentation/devicetree/bindings/regulator/
Dpalmas-pmic.txt3 The tps659038 for the AM57x class have OTP spins that
5 is not a need to add the OTP spins to the palmas driver. The
35 For ti,palmas-pmic - smps12, smps123, smps3 depending on OTP,
50 ti,smps-range - OTP has the wrong range set for the hardware so override
/Linux-v5.10/include/linux/ssb/
Dssb_driver_chipcommon.h47 #define SSB_CHIPCO_CAP_OTPS 0x00380000 /* OTP size */
61 #define SSB_CHIPCO_OTPS 0x0010 /* OTP status */
67 #define SSB_CHIPCO_OTPC 0x0014 /* OTP control */
74 #define SSB_CHIPCO_OTPP 0x0018 /* OTP prog */
398 #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
399 #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
400 #define SSB_CHIPCO_CHST_4325_OTP_SEL 2 /* OTP is powered up, no SPROM */
401 #define SSB_CHIPCO_CHST_4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */
548 /** OTP **/
550 /* OTP regions */
[all …]
/Linux-v5.10/drivers/iio/gyro/
Dmpu3050-core.c787 u8 otp[8]; in mpu3050_hw_init() local
812 /* Read out the 8 bytes of OTP (one-time-programmable) memory */ in mpu3050_hw_init()
818 sizeof(otp), in mpu3050_hw_init()
819 otp); in mpu3050_hw_init()
824 add_device_randomness(otp, sizeof(otp)); in mpu3050_hw_init()
830 (otp[1] << 8 | otp[0]) & 0x1fff, in mpu3050_hw_init()
832 ((otp[2] << 8 | otp[1]) & 0x03e0) >> 5, in mpu3050_hw_init()
834 ((otp[4] << 16 | otp[3] << 8 | otp[2]) & 0x3fffc) >> 2, in mpu3050_hw_init()
836 ((otp[5] << 8 | otp[4]) & 0x3ffc) >> 2, in mpu3050_hw_init()
838 ((otp[6] << 8 | otp[5]) & 0x0380) >> 7, in mpu3050_hw_init()
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/net/wireless/
Dmediatek,mt76.txt28 - mediatek,eeprom-merge-otp: Merge EEPROM data with OTP data. Can be used on
30 data should be pulled from the OTP ROM

1234567