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/Linux-v6.1/Documentation/devicetree/bindings/mtd/
Dmarvell-nand.txt1 Marvell NAND Flash Controller (NFC)
4 - compatible: can be one of the following:
5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
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Dmtk-nand.txt1 MTK SoCs NAND FLASH controller (NFC) DT binding
3 This file documents the device tree bindings for MTK SoCs NAND controllers.
5 the nand controller interface driver and the ECC engine driver.
10 1) NFC NAND Controller Interface (NFI):
13 The first part of NFC is NAND Controller Interface (NFI) HW.
15 - compatible: Should be one of
16 "mediatek,mt2701-nfc",
17 "mediatek,mt2712-nfc",
18 "mediatek,mt7622-nfc".
19 - reg: Base physical address and size of NFI.
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Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB NAND Controller
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
14 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
15 flash chips. It has a memory-mapped register interface for both control
25 -- Additional SoC-specific NAND controller properties --
27 The NAND controller is integrated differently on the variety of SoCs on which
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/Linux-v6.1/Documentation/driver-api/
Dmtdnand.rst2 MTD NAND Driver Programming Interface
10 The generic NAND driver supports almost all NAND and AG-AND based chips
15 board drivers or filesystem drivers suitable for NAND devices.
31 --------------------------
37 - [MTD Interface]
43 - [NAND Interface]
45 These functions are exported and provide the interface to the NAND
48 - [GENERIC]
53 - [DEFAULT]
55 Default functions provide hardware related functionality which is
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/Linux-v6.1/include/linux/mtd/
Dnand.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2017 - Free Electrons
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
18 * struct nand_memory_organization - Memory organization structure
19 * @bits_per_cell: number of bits per NAND cell
27 * @ntargets: total number of targets exposed by the NAND device
55 * struct nand_row_converter - Information needed to convert an absolute offset
67 * struct nand_pos - NAND position object
68 * @target: the NAND target/die
74 * These information are usually used by specific sub-layers to select the
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Drawnand.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
8 * Contains standard defines and IDs for NAND flash devices
17 #include <linux/mtd/nand.h>
29 /* The maximum number of NAND chips in an array */
50 * Standard NAND flash commands
73 #define NAND_CMD_NONE -1
82 #define NAND_DATA_IFACE_CHECK_ONLY -1
95 * Enable generic NAND 'page erased' check. This check is only done when
96 * ecc.correct() returns -EBADMSG.
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Dsh_flctl.h1 /* SPDX-License-Identifier: GPL-2.0
3 * SuperH FLCTL nand controller
18 #define FLCMNCR(f) (f->reg + 0x0)
19 #define FLCMDCR(f) (f->reg + 0x4)
20 #define FLCMCDR(f) (f->reg + 0x8)
21 #define FLADR(f) (f->reg + 0xC)
22 #define FLADR2(f) (f->reg + 0x3C)
23 #define FLDATAR(f) (f->reg + 0x10)
24 #define FLDTCNTR(f) (f->reg + 0x14)
25 #define FLINTDMACR(f) (f->reg + 0x18)
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Dplatnand.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
7 * Contains all platform NAND related definitions.
18 * struct platform_nand_chip - chip level device structure
26 * @part_probe_types: NULL-terminated array of probe types
40 * struct platform_nand_ctrl - controller level device structure
65 * struct platform_nand_data - container structure for platform-specific data
Dmtd.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org> et al.
15 #include <linux/nvmem-provider.h>
17 #include <mtd/mtd-abi.h>
21 #define MTD_FAIL_ADDR_UNKNOWN -1LL
50 * struct mtd_oob_ops - oob operation operands
61 * @datbuf: data buffer - if NULL only oob data are read/written
65 * one go. If you try to do that on such an MTD device, -EINVAL will be
67 * devices you should split the write request into several sub-requests when the
83 * struct mtd_oob_region - oob region definition
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/Linux-v6.1/drivers/mtd/nand/raw/
Dfsmc_nand.c1 // SPDX-License-Identifier: GPL-2.0
5 * Driver for NAND portions
11 * Based on drivers/mtd/nand/nomadik_nand.c (removed in v3.8)
20 #include <linux/dma-direction.h>
21 #include <linux/dma-mapping.h>
29 #include <linux/mtd/nand-ecc-sw-hamming.h>
37 #include <mtd/mtd-abi.h>
61 /* fsmc controller registers for NAND flash */
99 * TOUDEL = 7ns (Output delay from the flip-flops to the board)
120 * struct fsmc_nand_data - structure for FSMC NAND device state
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Dsunxi_nand.c1 // SPDX-License-Identifier: GPL-2.0+
6 * https://github.com/yuq/sunxi-nfc-mtd
9 * https://github.com/hno/Allwinner-Info
16 #include <linux/dma-mapping.h>
71 #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
108 #define NFC_ADR_NUM(x) (((x) - 1) << 16)
162 * struct sunxi_nand_chip_sel - stores information related to NAND Chip Select
164 * @cs: the NAND CS id used to communicate with a NAND Chip
165 * @rb: the Ready/Busy pin ID. -1 means no R/B pin connected to the NFC
173 * struct sunxi_nand_hw_ecc - stores information related to HW ECC support
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Dcadence-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence NAND flash controller driver
12 #include <linux/dma-mapping.h>
24 * - PIO - can work in master or slave DMA
25 * - CDMA - needs Master DMA for accessing command descriptors.
26 * - Generic mode - can use only slave DMA.
29 * on NAND flash memory. Driver uses CDMA mode for
115 /* Size of not-last data sector. */
159 /* Support for NV-DDR2/3 work mode. */
161 /* Support for NV-DDR work mode. */
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Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell NAND flash controller driver
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
9 * This NAND controller driver handles two versions of the hardware,
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
28 * +-------------------------------------------------------------+
30 * +-------------------------------------------------------------+
39 * +-----------------------------------------
41 * +-----------------------------------------
43 * -------------------------------------------
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Darasan-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
3 * Arasan NAND Flash Controller Driver
5 * Copyright (C) 2014 - 2020 Xilinx, Inc.
17 #include <linux/dma-mapping.h>
114 #define ANFC_MAX_PKT_SIZE (SZ_2K - 1)
124 * struct anfc_op - Defines how to execute an operation
150 * struct anand - Defines the NAND chip related information
151 * @node: Used to store NAND chips into a list
152 * @chip: NAND chip information structure
153 * @rb: Ready-busy line
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Dnand_base.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * This is the generic MTD driver for NAND flash devices. It should be
5 * capable of working with almost all NAND chips currently available.
8 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
21 * Check, if mtd->ecctype should be set to MTD_ECC_HW
37 #include <linux/mtd/nand.h>
38 #include <linux/mtd/nand-ecc-sw-hamming.h>
39 #include <linux/mtd/nand-ecc-sw-bch.h>
53 int lastpage = (mtd->erasesize / mtd->writesize) - 1; in nand_pairing_dist3_get_info()
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/Linux-v6.1/fs/jffs2/
DREADME.Locking3 ---------------------------
11 ---------
13 The alloc_sem is a per-filesystem mutex, used primarily to ensure
24 which they belong. This is for the benefit of NAND flash - adding new
26 until this happens we ensure that any data in the write-buffer at the
28 was written afterwards. Hence, we can ensure the newly-obsoleted nodes
29 don't actually get erased until the write-buffer has been flushed to
32 With the introduction of NAND flash support and the write-buffer,
33 the alloc_sem is also used to protect the wbuf-related members of the
37 Ordering constraints: See f->sem.
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/Linux-v6.1/drivers/pinctrl/
Dpinctrl-xway.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/pinctrl/pinmux-xway.c
4 * based on linux/drivers/pinctrl/pinmux-pxa910.c
21 #include "pinctrl-lantiq.h"
110 /* --------- DEPRECATED: xr9 related code --------- */
111 /* ---------- use xrx100/xrx200 instead ---------- */
249 GRP_MUX("nand ale", EBU, pins_nand_ale),
250 GRP_MUX("nand cs1", EBU, pins_nand_cs1),
251 GRP_MUX("nand cle", EBU, pins_nand_cle),
277 GRP_MUX("nand rdy", EBU, pins_nand_rdy),
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/Linux-v6.1/arch/arm/mach-s3c/
Ds3c2412.c1 // SPDX-License-Identifier: GPL-2.0
28 #include <asm/proc-fns.h>
33 #include "regs-clock.h"
34 #include "regs-gpio.h"
41 #include "nand-core-s3c24xx.h"
42 #include "regs-dsc-s3c24xx.h"
43 #include "s3c2412-power.h"
80 s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources, cfg, no); in s3c2412_init_uarts()
83 s3c_device_sdi.name = "s3c2412-sdi"; in s3c2412_init_uarts()
84 s3c_device_lcd.name = "s3c2412-lcd"; in s3c2412_init_uarts()
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/Linux-v6.1/Documentation/arm/samsung-s3c24xx/
Doverview.rst8 ------------
10 The Samsung S3C24XX range of ARM9 System-on-Chip CPUs are supported
21 included under the arch/arm/mach-s3c directory. Note, while core
27 -------------
38 ------
41 platform code contained in arch/arm/mach-s3c with headers in
42 arch/arm/mach-s3c/include
44 arch/arm/mach-s3c:
54 this directory, the name becomes invalid. We stick to s3c2440-<x>
62 --------
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/Linux-v6.1/Documentation/networking/devlink/
Diosm.rst1 .. SPDX-License-Identifier: GPL-2.0
13 The ``iosm`` driver implements the following driver-specific parameters.
15 .. list-table:: Driver-specific parameters implemented
18 * - Name
19 - Type
20 - Mode
21 - Description
22 * - ``erase_full_flash``
23 - u8
24 - runtime
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/Linux-v6.1/include/linux/mfd/syscon/
Datmel-smc.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
20 ((layout)->timing_regs_offset + ((cs) * 0x14))
23 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
26 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x8)
34 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x10)
53 #define ATMEL_SMC_MODE_TDF(x) (((x) - 1) << 16)
65 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0xc)
80 * struct atmel_smc_cs_conf - SMC CS config as described in the datasheet.
84 * @timings: advanced NAND related timings (only applicable to HSMC)
/Linux-v6.1/Documentation/leds/
Dleds-class.rst8 of the LED (taking a value 0-max_brightness). Most LEDs don't have hardware
9 brightness support so will just be turned on for non-zero brightness settings.
14 existing subsystems with minimal additional code. Examples are the disk-activity,
15 nand-disk and sharpsl-charge triggers. With led triggers disabled, the code
48 - devicename:
51 than to the hardware; the information related to the product and the bus
57 - color:
59 include/dt-bindings/leds/common.h.
61 - function:
63 include/dt-bindings/leds/common.h.
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/Linux-v6.1/drivers/memory/
Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
32 #include <linux/omap-gpmc.h>
36 #include <linux/platform_data/mtd-nand-omap2.h>
38 #define DEVICE_NAME "omap-gpmc"
189 #define GPMC_NR_NAND_IRQS 2 /* number of NAND specific IRQs */
249 /* Define chip-selects as reserved by default until probe completes */
297 * gpmc_get_clk_period - get period of selected clock domain in ps
334 return (time_ns * 1000 + tick_ps - 1) / tick_ps; in gpmc_ns_to_clk_ticks()
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/Linux-v6.1/arch/arm/mach-omap1/
Dboard-ams-delta.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap1/board-ams-delta.c
5 * Modified from board-generic.c
20 #include <linux/mtd/nand-gpio.h>
30 #include <linux/platform_data/gpio-omap.h>
31 #include <linux/soc/ti/omap1-mux.h>
34 #include <asm/mach-types.h>
38 #include <linux/platform_data/keypad-omap.h>
42 #include "ams-delta-fiq.h"
43 #include "board-ams-delta.h"
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/Linux-v6.1/drivers/media/platform/marvell/
Dcafe-driver.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * Copyright 2006-11 One Laptop Per Child Association, Inc.
11 * Copyright 2006-11 Jonathan Corbet <corbet@lwn.net>
28 #include <media/v4l2-device.h>
36 #include "mcam-core.h"
57 * Most of the camera controller registers are defined in mcam-core.h,
82 #define TWSIC0_MODE 0x00000002 /* 1 = 16-bit, 0 = 8-bit */
127 * Debugging and related.
130 dev_err(&(cam)->pdev->dev, fmt, ##arg);
132 dev_warn(&(cam)->pdev->dev, fmt, ##arg);
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