Lines Matching +full:nand +full:- +full:related
1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell NAND flash controller driver
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
9 * This NAND controller driver handles two versions of the hardware,
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
28 * +-------------------------------------------------------------+
30 * +-------------------------------------------------------------+
39 * +-----------------------------------------
41 * +-----------------------------------------
43 * -------------------------------------------
45 * -------------------------------------------
47 * --------------------------------------------+
49 * --------------------------------------------+
58 * - It can only read 2k at a time. To overcome this limitation, the
61 * - The ECC strength in BCH mode cannot be tuned. It is fixed 16
66 * - The controller will always treat data bytes, free OOB bytes
71 * - Because of these weird layouts, the Bad Block Markers can be
89 #include <linux/dma-mapping.h>
90 #include <linux/dma/pxa-dma.h>
91 #include <linux/platform_data/mtd-nand-pxa3xx.h>
111 /* System control registers/bits to enable the NAND controller on some SoCs */
122 /* NAND controller data flash control register */
141 /* NAND interface timing parameter 0 register */
155 /* NAND interface timing parameter 1 register */
164 /* NAND controller status register */
171 #define NDSR_CMDD(cs) BIT(8 - cs)
175 /* NAND ECC control register */
179 /* NAND controller data buffer register */
182 /* NAND controller command buffer 0 register */
195 /* NAND controller command buffer 1 register */
200 /* NAND controller command buffer 2 register */
205 /* NAND controller command buffer 3 register */
210 /* NAND controller command buffer 0 register 'type' and 'xtype' fields */
230 * struct marvell_hw_ecc_layout - layout of Marvell ECC
234 * per subpage, and depending on a the desired strength needed by the NAND chip,
243 * @full_chunk_cnt: Number of full-sized chunks, which is the number of
284 /* Layouts explained in AN-379_Marvell_SoC_NFC_ECC */
297 * struct marvell_nand_chip_sel - CS line description
299 * The Nand Flash Controller has up to 4 CE and 2 RB pins. The CE selection
319 * struct marvell_nand_chip - stores NAND chip device related information
321 * @chip: Base NAND chip structure
322 * @node: Used to store NAND chips into a list
323 * @layout: NAND layout when using hardware ECC
324 * @ndcr: Controller register value for this NAND chip
325 * @ndtr0: Timing registers 0 value for this NAND chip
326 * @ndtr1: Timing registers 1 value for this NAND chip
329 * @nsels: Number of CS lines required by the NAND chip
351 *nand) in to_nand_sel()
353 return &nand->sels[nand->selected_die]; in to_nand_sel()
357 * struct marvell_nfc_caps - NAND controller capabilities for distinction
363 * system controller (ie. to enable the NAND controller)
381 * struct marvell_nfc - stores Marvell NAND controller information
385 * @regs: NAND controller registers
388 * @complete: Completion object to wait for NAND controller events
390 * @chips: List containing all the NAND chips attached to
391 * this NAND controller
393 * @caps: NAND controller capabilities for each compatible string
396 * @dma_buf: 32-bit aligned buffer for DMA transfers (NFCv1 only)
422 * struct marvell_nfc_timings - NAND controller timings expressed in NAND
454 * TO_CYCLES() - Derives a duration in numbers of clock cycles.
456 * @ps: Duration in pico-seconds
457 * @period_ns: Clock period in nano-seconds
459 * Convert the duration in nano-seconds, then divide by the period and
467 * struct marvell_nfc_op - filled during the parsing of the ->exec_op()
513 reg = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_disable_int()
514 writel_relaxed(reg | int_mask, nfc->regs + NDCR); in marvell_nfc_disable_int()
522 reg = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_enable_int()
523 writel_relaxed(reg & ~int_mask, nfc->regs + NDCR); in marvell_nfc_enable_int()
530 reg = readl_relaxed(nfc->regs + NDSR); in marvell_nfc_clear_int()
531 writel_relaxed(int_mask, nfc->regs + NDSR); in marvell_nfc_clear_int()
539 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_force_byte_access()
543 * Callers of this function do not verify if the NAND is using a 16-bit in marvell_nfc_force_byte_access()
544 * an 8-bit bus for normal operations, so we need to take care of that in marvell_nfc_force_byte_access()
545 * here by leaving the configuration unchanged if the NAND does not have in marvell_nfc_force_byte_access()
548 if (!(chip->options & NAND_BUSWIDTH_16)) in marvell_nfc_force_byte_access()
551 ndcr = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_force_byte_access()
558 writel_relaxed(ndcr, nfc->regs + NDCR); in marvell_nfc_force_byte_access()
563 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_wait_ndrun()
571 ret = readl_relaxed_poll_timeout(nfc->regs + NDCR, val, in marvell_nfc_wait_ndrun()
575 dev_err(nfc->dev, "Timeout on NAND controller run mode\n"); in marvell_nfc_wait_ndrun()
576 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, in marvell_nfc_wait_ndrun()
577 nfc->regs + NDCR); in marvell_nfc_wait_ndrun()
587 * - call marvell_nfc_prepare_cmd()
588 * -> activate the ND_RUN bit that will kind of 'start a job'
589 * -> wait the signal indicating the NFC is waiting for a command
590 * - send the command (cmd and address cycles)
591 * - enventually send or receive the data
592 * - call marvell_nfc_end_cmd() with the corresponding flag
593 * -> wait the flag to be triggered or cancel the job with a timeout
596 * specialized functions responsible for executing the actual NAND
601 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_prepare_cmd()
608 dev_err(nfc->dev, "Last operation did not succeed\n"); in marvell_nfc_prepare_cmd()
612 ndcr = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_prepare_cmd()
613 writel_relaxed(readl(nfc->regs + NDSR), nfc->regs + NDSR); in marvell_nfc_prepare_cmd()
616 writel_relaxed(ndcr | NDCR_ND_RUN, nfc->regs + NDCR); in marvell_nfc_prepare_cmd()
617 ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val, in marvell_nfc_prepare_cmd()
621 dev_err(nfc->dev, "Timeout on WRCMDRE\n"); in marvell_nfc_prepare_cmd()
622 return -ETIMEDOUT; in marvell_nfc_prepare_cmd()
626 writel_relaxed(NDSR_WRCMDREQ, nfc->regs + NDSR); in marvell_nfc_prepare_cmd()
635 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_send_cmd()
637 dev_dbg(nfc->dev, "\nNDCR: 0x%08x\n" in marvell_nfc_send_cmd()
639 (u32)readl_relaxed(nfc->regs + NDCR), nfc_op->ndcb[0], in marvell_nfc_send_cmd()
640 nfc_op->ndcb[1], nfc_op->ndcb[2], nfc_op->ndcb[3]); in marvell_nfc_send_cmd()
642 writel_relaxed(to_nand_sel(marvell_nand)->ndcb0_csel | nfc_op->ndcb[0], in marvell_nfc_send_cmd()
643 nfc->regs + NDCB0); in marvell_nfc_send_cmd()
644 writel_relaxed(nfc_op->ndcb[1], nfc->regs + NDCB0); in marvell_nfc_send_cmd()
645 writel(nfc_op->ndcb[2], nfc->regs + NDCB0); in marvell_nfc_send_cmd()
651 if (nfc_op->ndcb[0] & NDCB0_LEN_OVRD || in marvell_nfc_send_cmd()
652 NDCB0_ADDR_GET_NUM_CYC(nfc_op->ndcb[0]) >= 6) { in marvell_nfc_send_cmd()
653 if (!WARN_ON_ONCE(!nfc->caps->is_nfcv2)) in marvell_nfc_send_cmd()
654 writel(nfc_op->ndcb[3], nfc->regs + NDCB0); in marvell_nfc_send_cmd()
661 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_end_cmd()
665 ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val, in marvell_nfc_end_cmd()
670 dev_err(nfc->dev, "Timeout on %s (NDSR: 0x%08x)\n", in marvell_nfc_end_cmd()
672 if (nfc->dma_chan) in marvell_nfc_end_cmd()
673 dmaengine_terminate_all(nfc->dma_chan); in marvell_nfc_end_cmd()
681 if (nfc->use_dma && (readl_relaxed(nfc->regs + NDCR) & NDCR_DMA_EN)) in marvell_nfc_end_cmd()
684 writel_relaxed(flag, nfc->regs + NDSR); in marvell_nfc_end_cmd()
692 int cs_flag = NDSR_CMDD(to_nand_sel(marvell_nand)->ndcb0_csel); in marvell_nfc_wait_cmdd()
705 st = readl_relaxed(nfc->regs + NDSR); in marvell_nfc_poll_status()
715 return -ETIMEDOUT; in marvell_nfc_poll_status()
720 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_wait_op()
729 if (mtd->oops_panic_write) { in marvell_nfc_wait_op()
734 init_completion(&nfc->complete); in marvell_nfc_wait_op()
737 ret = wait_for_completion_timeout(&nfc->complete, in marvell_nfc_wait_op()
748 dev_err(nfc->dev, "Timeout waiting for RB signal\n"); in marvell_nfc_wait_op()
749 return -ETIMEDOUT; in marvell_nfc_wait_op()
759 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_select_target()
766 ndcr_generic = readl_relaxed(nfc->regs + NDCR) & in marvell_nfc_select_target()
768 writel_relaxed(ndcr_generic | marvell_nand->ndcr, nfc->regs + NDCR); in marvell_nfc_select_target()
773 if (chip == nfc->selected_chip && die_nr == marvell_nand->selected_die) in marvell_nfc_select_target()
776 writel_relaxed(marvell_nand->ndtr0, nfc->regs + NDTR0); in marvell_nfc_select_target()
777 writel_relaxed(marvell_nand->ndtr1, nfc->regs + NDTR1); in marvell_nfc_select_target()
779 nfc->selected_chip = chip; in marvell_nfc_select_target()
780 marvell_nand->selected_die = die_nr; in marvell_nfc_select_target()
786 u32 st = readl_relaxed(nfc->regs + NDSR); in marvell_nfc_isr()
787 u32 ien = (~readl_relaxed(nfc->regs + NDCR)) & NDCR_ALL_INT; in marvell_nfc_isr()
802 complete(&nfc->complete); in marvell_nfc_isr()
807 /* HW ECC related functions */
810 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_enable_hw_ecc()
811 u32 ndcr = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_enable_hw_ecc()
814 writel_relaxed(ndcr | NDCR_ECC_EN, nfc->regs + NDCR); in marvell_nfc_enable_hw_ecc()
820 if (chip->ecc.algo == NAND_ECC_ALGO_BCH) in marvell_nfc_enable_hw_ecc()
821 writel_relaxed(NDECCCTRL_BCH_EN, nfc->regs + NDECCCTRL); in marvell_nfc_enable_hw_ecc()
827 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_disable_hw_ecc()
828 u32 ndcr = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_disable_hw_ecc()
831 writel_relaxed(ndcr & ~NDCR_ECC_EN, nfc->regs + NDCR); in marvell_nfc_disable_hw_ecc()
832 if (chip->ecc.algo == NAND_ECC_ALGO_BCH) in marvell_nfc_disable_hw_ecc()
833 writel_relaxed(0, nfc->regs + NDECCCTRL); in marvell_nfc_disable_hw_ecc()
837 /* DMA related helpers */
842 reg = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_enable_dma()
843 writel_relaxed(reg | NDCR_DMA_EN, nfc->regs + NDCR); in marvell_nfc_enable_dma()
850 reg = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_disable_dma()
851 writel_relaxed(reg & ~NDCR_DMA_EN, nfc->regs + NDCR); in marvell_nfc_disable_dma()
867 sg_init_one(&sg, nfc->dma_buf, dma_len); in marvell_nfc_xfer_data_dma()
868 ret = dma_map_sg(nfc->dma_chan->device->dev, &sg, 1, direction); in marvell_nfc_xfer_data_dma()
870 dev_err(nfc->dev, "Could not map DMA S/G list\n"); in marvell_nfc_xfer_data_dma()
871 return -ENXIO; in marvell_nfc_xfer_data_dma()
874 tx = dmaengine_prep_slave_sg(nfc->dma_chan, &sg, 1, in marvell_nfc_xfer_data_dma()
879 dev_err(nfc->dev, "Could not prepare DMA S/G list\n"); in marvell_nfc_xfer_data_dma()
880 dma_unmap_sg(nfc->dma_chan->device->dev, &sg, 1, direction); in marvell_nfc_xfer_data_dma()
881 return -ENXIO; in marvell_nfc_xfer_data_dma()
888 return -EIO; in marvell_nfc_xfer_data_dma()
890 dma_async_issue_pending(nfc->dma_chan); in marvell_nfc_xfer_data_dma()
891 ret = marvell_nfc_wait_cmdd(nfc->selected_chip); in marvell_nfc_xfer_data_dma()
892 dma_unmap_sg(nfc->dma_chan->device->dev, &sg, 1, direction); in marvell_nfc_xfer_data_dma()
895 dev_err(nfc->dev, "Timeout waiting for DMA (status: %d)\n", in marvell_nfc_xfer_data_dma()
896 dmaengine_tx_status(nfc->dma_chan, cookie, NULL)); in marvell_nfc_xfer_data_dma()
897 dmaengine_terminate_all(nfc->dma_chan); in marvell_nfc_xfer_data_dma()
898 return -ETIMEDOUT; in marvell_nfc_xfer_data_dma()
912 ioread32_rep(nfc->regs + NDDB, in + i, FIFO_REP(FIFO_DEPTH)); in marvell_nfc_xfer_data_in_pio()
917 ioread32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH)); in marvell_nfc_xfer_data_in_pio()
932 iowrite32_rep(nfc->regs + NDDB, out + i, FIFO_REP(FIFO_DEPTH)); in marvell_nfc_xfer_data_out_pio()
938 iowrite32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH)); in marvell_nfc_xfer_data_out_pio()
966 spare, spare_len, chip->ecc.strength); in marvell_nfc_check_empty_chunk()
968 mtd->ecc_stats.failed++; in marvell_nfc_check_empty_chunk()
973 mtd->ecc_stats.corrected += bf; in marvell_nfc_check_empty_chunk()
979 * mtd->ecc_stats.corrected is updated, as well as max_bitflips, however
980 * mtd->ecc_stats.failure is not, the function will instead return a non-zero
988 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_hw_ecc_check_bitflips()
992 ndsr = readl_relaxed(nfc->regs + NDSR); in marvell_nfc_hw_ecc_check_bitflips()
996 writel_relaxed(ndsr, nfc->regs + NDSR); in marvell_nfc_hw_ecc_check_bitflips()
999 * Do not increment ->ecc_stats.failed now, instead, return a in marvell_nfc_hw_ecc_check_bitflips()
1000 * non-zero value to indicate that this chunk was apparently in marvell_nfc_hw_ecc_check_bitflips()
1005 return -EBADMSG; in marvell_nfc_hw_ecc_check_bitflips()
1010 writel_relaxed(ndsr, nfc->regs + NDSR); in marvell_nfc_hw_ecc_check_bitflips()
1012 if (chip->ecc.algo == NAND_ECC_ALGO_BCH) in marvell_nfc_hw_ecc_check_bitflips()
1019 mtd->ecc_stats.corrected += bf; in marvell_nfc_hw_ecc_check_bitflips()
1031 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_hw_ecc_hmg_do_read_page()
1032 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_hmg_do_read_page()
1035 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | in marvell_nfc_hw_ecc_hmg_do_read_page()
1042 unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0); in marvell_nfc_hw_ecc_hmg_do_read_page()
1046 if (nfc->caps->is_nfcv2) in marvell_nfc_hw_ecc_hmg_do_read_page()
1065 if (nfc->use_dma) { in marvell_nfc_hw_ecc_hmg_do_read_page()
1067 lt->data_bytes + oob_bytes); in marvell_nfc_hw_ecc_hmg_do_read_page()
1068 memcpy(data_buf, nfc->dma_buf, lt->data_bytes); in marvell_nfc_hw_ecc_hmg_do_read_page()
1069 memcpy(oob_buf, nfc->dma_buf + lt->data_bytes, oob_bytes); in marvell_nfc_hw_ecc_hmg_do_read_page()
1071 marvell_nfc_xfer_data_in_pio(nfc, data_buf, lt->data_bytes); in marvell_nfc_hw_ecc_hmg_do_read_page()
1082 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_hmg_read_page_raw()
1083 return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, in marvell_nfc_hw_ecc_hmg_read_page_raw()
1090 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_hmg_read_page()
1091 unsigned int full_sz = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; in marvell_nfc_hw_ecc_hmg_read_page()
1095 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_hmg_read_page()
1097 marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, false, in marvell_nfc_hw_ecc_hmg_read_page()
1111 return -ENOMEM; in marvell_nfc_hw_ecc_hmg_read_page()
1114 lt->data_bytes, true, page); in marvell_nfc_hw_ecc_hmg_read_page()
1124 * it appears before the ECC bytes when reading), the ->read_oob_raw() function
1125 * also stands for ->read_oob().
1131 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_hmg_read_oob_raw()
1132 return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, in marvell_nfc_hw_ecc_hmg_read_oob_raw()
1145 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_hw_ecc_hmg_do_write_page()
1146 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_hmg_do_write_page()
1149 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | in marvell_nfc_hw_ecc_hmg_do_write_page()
1156 unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0); in marvell_nfc_hw_ecc_hmg_do_write_page()
1160 if (nfc->caps->is_nfcv2) in marvell_nfc_hw_ecc_hmg_do_write_page()
1174 if (nfc->use_dma) { in marvell_nfc_hw_ecc_hmg_do_write_page()
1175 memcpy(nfc->dma_buf, data_buf, lt->data_bytes); in marvell_nfc_hw_ecc_hmg_do_write_page()
1176 memcpy(nfc->dma_buf + lt->data_bytes, oob_buf, oob_bytes); in marvell_nfc_hw_ecc_hmg_do_write_page()
1177 marvell_nfc_xfer_data_dma(nfc, DMA_TO_DEVICE, lt->data_bytes + in marvell_nfc_hw_ecc_hmg_do_write_page()
1178 lt->ecc_bytes + lt->spare_bytes); in marvell_nfc_hw_ecc_hmg_do_write_page()
1180 marvell_nfc_xfer_data_out_pio(nfc, data_buf, lt->data_bytes); in marvell_nfc_hw_ecc_hmg_do_write_page()
1189 PSEC_TO_MSEC(sdr->tPROG_max)); in marvell_nfc_hw_ecc_hmg_do_write_page()
1197 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_hmg_write_page_raw()
1198 return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi, in marvell_nfc_hw_ecc_hmg_write_page_raw()
1208 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_hmg_write_page()
1210 ret = marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi, in marvell_nfc_hw_ecc_hmg_write_page()
1219 * it appears before the ECC bytes when reading), the ->write_oob_raw() function
1220 * also stands for ->write_oob().
1228 memset(buf, 0xFF, mtd->writesize); in marvell_nfc_hw_ecc_hmg_write_oob_raw()
1230 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_hmg_write_oob_raw()
1231 return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi, in marvell_nfc_hw_ecc_hmg_write_oob_raw()
1240 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_bch_read_page_raw()
1241 u8 *oob = chip->oob_poi; in marvell_nfc_hw_ecc_bch_read_page_raw()
1242 int chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1243 int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) + in marvell_nfc_hw_ecc_bch_read_page_raw()
1244 lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1245 int data_len = lt->data_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1246 int spare_len = lt->spare_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1247 int ecc_len = lt->ecc_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1250 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_bch_read_page_raw()
1253 memset(chip->oob_poi, 0xFF, mtd->oobsize); in marvell_nfc_hw_ecc_bch_read_page_raw()
1257 for (chunk = 0; chunk < lt->nchunks; chunk++) { in marvell_nfc_hw_ecc_bch_read_page_raw()
1259 if (chunk >= lt->full_chunk_cnt) { in marvell_nfc_hw_ecc_bch_read_page_raw()
1260 data_len = lt->last_data_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1261 spare_len = lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1262 ecc_len = lt->last_ecc_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1267 buf + (lt->data_bytes * chunk), in marvell_nfc_hw_ecc_bch_read_page_raw()
1271 nand_read_data_op(chip, oob + (lt->spare_bytes * chunk), in marvell_nfc_hw_ecc_bch_read_page_raw()
1276 (ALIGN(lt->ecc_bytes, 32) * chunk), in marvell_nfc_hw_ecc_bch_read_page_raw()
1289 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_hw_ecc_bch_read_chunk()
1290 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_bch_read_chunk()
1294 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | in marvell_nfc_hw_ecc_bch_read_chunk()
1316 else if (chunk < lt->nchunks - 1) in marvell_nfc_hw_ecc_bch_read_chunk()
1328 * Drain the FIFO, 8 32-bit reads at a time, and skip in marvell_nfc_hw_ecc_bch_read_chunk()
1355 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_bch_read_page()
1356 int data_len = lt->data_bytes, spare_len = lt->spare_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1357 u8 *data = buf, *spare = chip->oob_poi; in marvell_nfc_hw_ecc_bch_read_page()
1362 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_bch_read_page()
1370 memset(chip->oob_poi, 0xFF, mtd->oobsize); in marvell_nfc_hw_ecc_bch_read_page()
1374 for (chunk = 0; chunk < lt->nchunks; chunk++) { in marvell_nfc_hw_ecc_bch_read_page()
1376 if (chunk >= lt->full_chunk_cnt) { in marvell_nfc_hw_ecc_bch_read_page()
1377 data_len = lt->last_data_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1378 spare_len = lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1400 * the controller in normal mode and must be re-read in raw mode. To in marvell_nfc_hw_ecc_bch_read_page()
1402 * user should re-read the page in raw mode if ECC bytes are required. in marvell_nfc_hw_ecc_bch_read_page()
1406 * In case there is any subpage read error, we usually re-read only ECC in marvell_nfc_hw_ecc_bch_read_page()
1413 * this strange behavior, the whole page is re-read in raw mode, not in marvell_nfc_hw_ecc_bch_read_page()
1416 for (chunk = 0; chunk < lt->nchunks; chunk++) { in marvell_nfc_hw_ecc_bch_read_page()
1425 data_off_in_page = chunk * (lt->data_bytes + lt->spare_bytes + in marvell_nfc_hw_ecc_bch_read_page()
1426 lt->ecc_bytes); in marvell_nfc_hw_ecc_bch_read_page()
1428 (chunk < lt->full_chunk_cnt ? lt->data_bytes : in marvell_nfc_hw_ecc_bch_read_page()
1429 lt->last_data_bytes); in marvell_nfc_hw_ecc_bch_read_page()
1431 (chunk < lt->full_chunk_cnt ? lt->spare_bytes : in marvell_nfc_hw_ecc_bch_read_page()
1432 lt->last_spare_bytes); in marvell_nfc_hw_ecc_bch_read_page()
1434 data_off = chunk * lt->data_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1435 spare_off = chunk * lt->spare_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1436 ecc_off = (lt->full_chunk_cnt * lt->spare_bytes) + in marvell_nfc_hw_ecc_bch_read_page()
1437 lt->last_spare_bytes + in marvell_nfc_hw_ecc_bch_read_page()
1438 (chunk * (lt->ecc_bytes + 2)); in marvell_nfc_hw_ecc_bch_read_page()
1440 data_len = chunk < lt->full_chunk_cnt ? lt->data_bytes : in marvell_nfc_hw_ecc_bch_read_page()
1441 lt->last_data_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1442 spare_len = chunk < lt->full_chunk_cnt ? lt->spare_bytes : in marvell_nfc_hw_ecc_bch_read_page()
1443 lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1444 ecc_len = chunk < lt->full_chunk_cnt ? lt->ecc_bytes : in marvell_nfc_hw_ecc_bch_read_page()
1445 lt->last_ecc_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1448 * Only re-read the ECC bytes, unless we are using the 2k/8b in marvell_nfc_hw_ecc_bch_read_page()
1451 * case, re-read the entire page. in marvell_nfc_hw_ecc_bch_read_page()
1453 if (lt->writesize == 2048 && lt->strength == 8) { in marvell_nfc_hw_ecc_bch_read_page()
1458 chip->oob_poi + spare_off, spare_len, in marvell_nfc_hw_ecc_bch_read_page()
1463 chip->oob_poi + ecc_off, ecc_len, in marvell_nfc_hw_ecc_bch_read_page()
1468 chip->oob_poi + spare_off, spare_len, in marvell_nfc_hw_ecc_bch_read_page()
1469 chip->oob_poi + ecc_off, ecc_len, in marvell_nfc_hw_ecc_bch_read_page()
1480 return chip->ecc.read_page_raw(chip, buf, true, page); in marvell_nfc_hw_ecc_bch_read_oob_raw()
1487 return chip->ecc.read_page(chip, buf, true, page); in marvell_nfc_hw_ecc_bch_read_oob()
1495 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_bch_write_page_raw()
1496 int full_chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1497 int data_len = lt->data_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1498 int spare_len = lt->spare_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1499 int ecc_len = lt->ecc_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1501 int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) + in marvell_nfc_hw_ecc_bch_write_page_raw()
1502 lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1505 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_bch_write_page_raw()
1509 for (chunk = 0; chunk < lt->nchunks; chunk++) { in marvell_nfc_hw_ecc_bch_write_page_raw()
1510 if (chunk >= lt->full_chunk_cnt) { in marvell_nfc_hw_ecc_bch_write_page_raw()
1511 data_len = lt->last_data_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1512 spare_len = lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1513 ecc_len = lt->last_ecc_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1521 nand_write_data_op(chip, buf + (chunk * lt->data_bytes), in marvell_nfc_hw_ecc_bch_write_page_raw()
1529 nand_write_data_op(chip, chip->oob_poi + spare_offset, in marvell_nfc_hw_ecc_bch_write_page_raw()
1534 nand_write_data_op(chip, chip->oob_poi + ecc_offset, in marvell_nfc_hw_ecc_bch_write_page_raw()
1551 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_hw_ecc_bch_write_chunk()
1552 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_bch_write_chunk()
1569 if (lt->nchunks == 1) in marvell_nfc_hw_ecc_bch_write_chunk()
1575 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | in marvell_nfc_hw_ecc_bch_write_chunk()
1579 } else if (chunk < lt->nchunks - 1) { in marvell_nfc_hw_ecc_bch_write_chunk()
1586 if (chunk == lt->nchunks - 1) in marvell_nfc_hw_ecc_bch_write_chunk()
1600 iowrite32_rep(nfc->regs + NDDB, data, FIFO_REP(data_len)); in marvell_nfc_hw_ecc_bch_write_chunk()
1601 iowrite32_rep(nfc->regs + NDDB, spare, FIFO_REP(spare_len)); in marvell_nfc_hw_ecc_bch_write_chunk()
1613 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_bch_write_page()
1615 const u8 *spare = chip->oob_poi; in marvell_nfc_hw_ecc_bch_write_page()
1616 int data_len = lt->data_bytes; in marvell_nfc_hw_ecc_bch_write_page()
1617 int spare_len = lt->spare_bytes; in marvell_nfc_hw_ecc_bch_write_page()
1620 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_bch_write_page()
1624 memset(chip->oob_poi, 0xFF, mtd->oobsize); in marvell_nfc_hw_ecc_bch_write_page()
1628 for (chunk = 0; chunk < lt->nchunks; chunk++) { in marvell_nfc_hw_ecc_bch_write_page()
1629 if (chunk >= lt->full_chunk_cnt) { in marvell_nfc_hw_ecc_bch_write_page()
1630 data_len = lt->last_data_bytes; in marvell_nfc_hw_ecc_bch_write_page()
1631 spare_len = lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_write_page()
1648 ret = marvell_nfc_wait_op(chip, PSEC_TO_MSEC(sdr->tPROG_max)); in marvell_nfc_hw_ecc_bch_write_page()
1664 memset(buf, 0xFF, mtd->writesize); in marvell_nfc_hw_ecc_bch_write_oob_raw()
1666 return chip->ecc.write_page_raw(chip, buf, true, page); in marvell_nfc_hw_ecc_bch_write_oob_raw()
1674 memset(buf, 0xFF, mtd->writesize); in marvell_nfc_hw_ecc_bch_write_oob()
1676 return chip->ecc.write_page(chip, buf, true, page); in marvell_nfc_hw_ecc_bch_write_oob()
1679 /* NAND framework ->exec_op() hooks and related helpers */
1685 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_parse_instructions()
1693 for (op_id = 0; op_id < subop->ninstrs; op_id++) { in marvell_nfc_parse_instructions()
1698 instr = &subop->instrs[op_id]; in marvell_nfc_parse_instructions()
1700 switch (instr->type) { in marvell_nfc_parse_instructions()
1703 nfc_op->ndcb[0] |= in marvell_nfc_parse_instructions()
1704 NDCB0_CMD1(instr->ctx.cmd.opcode); in marvell_nfc_parse_instructions()
1706 nfc_op->ndcb[0] |= in marvell_nfc_parse_instructions()
1707 NDCB0_CMD2(instr->ctx.cmd.opcode) | in marvell_nfc_parse_instructions()
1710 nfc_op->cle_ale_delay_ns = instr->delay_ns; in marvell_nfc_parse_instructions()
1717 addrs = &instr->ctx.addr.addrs[offset]; in marvell_nfc_parse_instructions()
1719 nfc_op->ndcb[0] |= NDCB0_ADDR_CYC(naddrs); in marvell_nfc_parse_instructions()
1722 nfc_op->ndcb[1] |= addrs[i] << (8 * i); in marvell_nfc_parse_instructions()
1725 nfc_op->ndcb[2] |= NDCB2_ADDR5_CYC(addrs[4]); in marvell_nfc_parse_instructions()
1727 nfc_op->ndcb[3] |= NDCB3_ADDR6_CYC(addrs[5]); in marvell_nfc_parse_instructions()
1729 nfc_op->ndcb[3] |= NDCB3_ADDR7_CYC(addrs[6]); in marvell_nfc_parse_instructions()
1731 nfc_op->cle_ale_delay_ns = instr->delay_ns; in marvell_nfc_parse_instructions()
1735 nfc_op->data_instr = instr; in marvell_nfc_parse_instructions()
1736 nfc_op->data_instr_idx = op_id; in marvell_nfc_parse_instructions()
1737 nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ); in marvell_nfc_parse_instructions()
1738 if (nfc->caps->is_nfcv2) { in marvell_nfc_parse_instructions()
1739 nfc_op->ndcb[0] |= in marvell_nfc_parse_instructions()
1743 nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH); in marvell_nfc_parse_instructions()
1745 nfc_op->data_delay_ns = instr->delay_ns; in marvell_nfc_parse_instructions()
1749 nfc_op->data_instr = instr; in marvell_nfc_parse_instructions()
1750 nfc_op->data_instr_idx = op_id; in marvell_nfc_parse_instructions()
1751 nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_WRITE); in marvell_nfc_parse_instructions()
1752 if (nfc->caps->is_nfcv2) { in marvell_nfc_parse_instructions()
1753 nfc_op->ndcb[0] |= in marvell_nfc_parse_instructions()
1757 nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH); in marvell_nfc_parse_instructions()
1759 nfc_op->data_delay_ns = instr->delay_ns; in marvell_nfc_parse_instructions()
1763 nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms; in marvell_nfc_parse_instructions()
1764 nfc_op->rdy_delay_ns = instr->delay_ns; in marvell_nfc_parse_instructions()
1774 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_xfer_data_pio()
1775 const struct nand_op_instr *instr = nfc_op->data_instr; in marvell_nfc_xfer_data_pio()
1776 unsigned int op_id = nfc_op->data_instr_idx; in marvell_nfc_xfer_data_pio()
1779 bool reading = (instr->type == NAND_OP_DATA_IN_INSTR); in marvell_nfc_xfer_data_pio()
1782 if (instr->ctx.data.force_8bit) in marvell_nfc_xfer_data_pio()
1786 u8 *in = instr->ctx.data.buf.in + offset; in marvell_nfc_xfer_data_pio()
1790 const u8 *out = instr->ctx.data.buf.out + offset; in marvell_nfc_xfer_data_pio()
1795 if (instr->ctx.data.force_8bit) in marvell_nfc_xfer_data_pio()
1809 reading = (nfc_op.data_instr->type == NAND_OP_DATA_IN_INSTR); in marvell_nfc_monolithic_access_exec()
1856 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_monolithic_access_exec()
1858 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, in marvell_nfc_monolithic_access_exec()
1859 nfc->regs + NDCR); in marvell_nfc_monolithic_access_exec()
1880 switch (subop->instrs[0].type) { in marvell_nfc_naked_access_exec()
1927 if (subop->instrs[0].type == NAND_OP_DATA_OUT_INSTR) { in marvell_nfc_naked_access_exec()
1928 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_naked_access_exec()
1930 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, in marvell_nfc_naked_access_exec()
1931 nfc->regs + NDCR); in marvell_nfc_naked_access_exec()
2153 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_exec_op()
2156 marvell_nfc_select_target(chip, op->cs); in marvell_nfc_exec_op()
2158 if (nfc->caps->is_nfcv2) in marvell_nfc_exec_op()
2174 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nand_ooblayout_ecc()
2177 return -ERANGE; in marvell_nand_ooblayout_ecc()
2179 oobregion->length = (lt->full_chunk_cnt * lt->ecc_bytes) + in marvell_nand_ooblayout_ecc()
2180 lt->last_ecc_bytes; in marvell_nand_ooblayout_ecc()
2181 oobregion->offset = mtd->oobsize - oobregion->length; in marvell_nand_ooblayout_ecc()
2190 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nand_ooblayout_free()
2193 return -ERANGE; in marvell_nand_ooblayout_free()
2199 if (mtd->writesize == SZ_4K && lt->data_bytes == SZ_2K) in marvell_nand_ooblayout_free()
2200 oobregion->offset = 6; in marvell_nand_ooblayout_free()
2202 oobregion->offset = 2; in marvell_nand_ooblayout_free()
2204 oobregion->length = (lt->full_chunk_cnt * lt->spare_bytes) + in marvell_nand_ooblayout_free()
2205 lt->last_spare_bytes - oobregion->offset; in marvell_nand_ooblayout_free()
2219 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nand_hw_ecc_controller_init()
2223 if (!nfc->caps->is_nfcv2 && in marvell_nand_hw_ecc_controller_init()
2224 (mtd->writesize + mtd->oobsize > MAX_CHUNK_SIZE)) { in marvell_nand_hw_ecc_controller_init()
2225 dev_err(nfc->dev, in marvell_nand_hw_ecc_controller_init()
2227 mtd->writesize, MAX_CHUNK_SIZE - mtd->oobsize); in marvell_nand_hw_ecc_controller_init()
2228 return -ENOTSUPP; in marvell_nand_hw_ecc_controller_init()
2231 to_marvell_nand(chip)->layout = NULL; in marvell_nand_hw_ecc_controller_init()
2234 if (mtd->writesize == l->writesize && in marvell_nand_hw_ecc_controller_init()
2235 ecc->size == l->chunk && ecc->strength == l->strength) { in marvell_nand_hw_ecc_controller_init()
2236 to_marvell_nand(chip)->layout = l; in marvell_nand_hw_ecc_controller_init()
2241 if (!to_marvell_nand(chip)->layout || in marvell_nand_hw_ecc_controller_init()
2242 (!nfc->caps->is_nfcv2 && ecc->strength > 1)) { in marvell_nand_hw_ecc_controller_init()
2243 dev_err(nfc->dev, in marvell_nand_hw_ecc_controller_init()
2245 ecc->strength, mtd->writesize); in marvell_nand_hw_ecc_controller_init()
2246 return -ENOTSUPP; in marvell_nand_hw_ecc_controller_init()
2249 /* Special care for the layout 2k/8-bit/512B */ in marvell_nand_hw_ecc_controller_init()
2250 if (l->writesize == 2048 && l->strength == 8) { in marvell_nand_hw_ecc_controller_init()
2251 if (mtd->oobsize < 128) { in marvell_nand_hw_ecc_controller_init()
2252 dev_err(nfc->dev, "Requested layout needs at least 128 OOB bytes\n"); in marvell_nand_hw_ecc_controller_init()
2253 return -ENOTSUPP; in marvell_nand_hw_ecc_controller_init()
2255 chip->bbt_options |= NAND_BBT_NO_OOB_BBM; in marvell_nand_hw_ecc_controller_init()
2260 ecc->steps = l->nchunks; in marvell_nand_hw_ecc_controller_init()
2261 ecc->size = l->data_bytes; in marvell_nand_hw_ecc_controller_init()
2263 if (ecc->strength == 1) { in marvell_nand_hw_ecc_controller_init()
2264 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in marvell_nand_hw_ecc_controller_init()
2265 ecc->read_page_raw = marvell_nfc_hw_ecc_hmg_read_page_raw; in marvell_nand_hw_ecc_controller_init()
2266 ecc->read_page = marvell_nfc_hw_ecc_hmg_read_page; in marvell_nand_hw_ecc_controller_init()
2267 ecc->read_oob_raw = marvell_nfc_hw_ecc_hmg_read_oob_raw; in marvell_nand_hw_ecc_controller_init()
2268 ecc->read_oob = ecc->read_oob_raw; in marvell_nand_hw_ecc_controller_init()
2269 ecc->write_page_raw = marvell_nfc_hw_ecc_hmg_write_page_raw; in marvell_nand_hw_ecc_controller_init()
2270 ecc->write_page = marvell_nfc_hw_ecc_hmg_write_page; in marvell_nand_hw_ecc_controller_init()
2271 ecc->write_oob_raw = marvell_nfc_hw_ecc_hmg_write_oob_raw; in marvell_nand_hw_ecc_controller_init()
2272 ecc->write_oob = ecc->write_oob_raw; in marvell_nand_hw_ecc_controller_init()
2274 chip->ecc.algo = NAND_ECC_ALGO_BCH; in marvell_nand_hw_ecc_controller_init()
2275 ecc->strength = 16; in marvell_nand_hw_ecc_controller_init()
2276 ecc->read_page_raw = marvell_nfc_hw_ecc_bch_read_page_raw; in marvell_nand_hw_ecc_controller_init()
2277 ecc->read_page = marvell_nfc_hw_ecc_bch_read_page; in marvell_nand_hw_ecc_controller_init()
2278 ecc->read_oob_raw = marvell_nfc_hw_ecc_bch_read_oob_raw; in marvell_nand_hw_ecc_controller_init()
2279 ecc->read_oob = marvell_nfc_hw_ecc_bch_read_oob; in marvell_nand_hw_ecc_controller_init()
2280 ecc->write_page_raw = marvell_nfc_hw_ecc_bch_write_page_raw; in marvell_nand_hw_ecc_controller_init()
2281 ecc->write_page = marvell_nfc_hw_ecc_bch_write_page; in marvell_nand_hw_ecc_controller_init()
2282 ecc->write_oob_raw = marvell_nfc_hw_ecc_bch_write_oob_raw; in marvell_nand_hw_ecc_controller_init()
2283 ecc->write_oob = marvell_nfc_hw_ecc_bch_write_oob; in marvell_nand_hw_ecc_controller_init()
2294 nanddev_get_ecc_requirements(&chip->base); in marvell_nand_ecc_init()
2295 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nand_ecc_init()
2298 if (ecc->engine_type != NAND_ECC_ENGINE_TYPE_NONE && in marvell_nand_ecc_init()
2299 (!ecc->size || !ecc->strength)) { in marvell_nand_ecc_init()
2300 if (requirements->step_size && requirements->strength) { in marvell_nand_ecc_init()
2301 ecc->size = requirements->step_size; in marvell_nand_ecc_init()
2302 ecc->strength = requirements->strength; in marvell_nand_ecc_init()
2304 dev_info(nfc->dev, in marvell_nand_ecc_init()
2306 ecc->size = 512; in marvell_nand_ecc_init()
2307 ecc->strength = 1; in marvell_nand_ecc_init()
2311 switch (ecc->engine_type) { in marvell_nand_ecc_init()
2320 if (!nfc->caps->is_nfcv2 && mtd->writesize != SZ_512 && in marvell_nand_ecc_init()
2321 mtd->writesize != SZ_2K) { in marvell_nand_ecc_init()
2322 dev_err(nfc->dev, "NFCv1 cannot write %d bytes pages\n", in marvell_nand_ecc_init()
2323 mtd->writesize); in marvell_nand_ecc_init()
2324 return -EINVAL; in marvell_nand_ecc_init()
2328 return -EINVAL; in marvell_nand_ecc_init()
2361 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_setup_interface()
2362 unsigned int period_ns = 1000000000 / clk_get_rate(nfc->core_clk) * 2; in marvell_nfc_setup_interface()
2372 * SDR timings are given in pico-seconds while NFC timings must be in marvell_nfc_setup_interface()
2373 * expressed in NAND controller clock cycles, which is half of the in marvell_nfc_setup_interface()
2382 nfc_tmg.tRP = TO_CYCLES(DIV_ROUND_UP(sdr->tRC_min, 2), period_ns) - 1; in marvell_nfc_setup_interface()
2384 nfc_tmg.tWP = TO_CYCLES(DIV_ROUND_UP(sdr->tWC_min, 2), period_ns) - 1; in marvell_nfc_setup_interface()
2386 nfc_tmg.tCS = TO_CYCLES(sdr->tCS_min, period_ns); in marvell_nfc_setup_interface()
2387 nfc_tmg.tCH = TO_CYCLES(sdr->tCH_min, period_ns) - 1; in marvell_nfc_setup_interface()
2388 nfc_tmg.tADL = TO_CYCLES(sdr->tADL_min, period_ns); in marvell_nfc_setup_interface()
2391 * logic. With non-EDO timings, this is MIN_RD_DEL_CNT clock cycles. In in marvell_nfc_setup_interface()
2395 read_delay = sdr->tRC_min >= 30000 ? in marvell_nfc_setup_interface()
2398 nfc_tmg.tAR = TO_CYCLES(sdr->tAR_min, period_ns); in marvell_nfc_setup_interface()
2404 nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min), in marvell_nfc_setup_interface()
2405 period_ns) - 2; in marvell_nfc_setup_interface()
2406 nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min), in marvell_nfc_setup_interface()
2413 if (nfc->caps->is_nfcv2) { in marvell_nfc_setup_interface()
2414 nfc_tmg.tR = TO_CYCLES(sdr->tWB_max, period_ns); in marvell_nfc_setup_interface()
2416 nfc_tmg.tR = TO_CYCLES64(sdr->tWB_max + sdr->tR_max, in marvell_nfc_setup_interface()
2419 nfc_tmg.tR = nfc_tmg.tCH - 3; in marvell_nfc_setup_interface()
2427 marvell_nand->ndtr0 = in marvell_nfc_setup_interface()
2436 marvell_nand->ndtr1 = in marvell_nfc_setup_interface()
2441 if (nfc->caps->is_nfcv2) { in marvell_nfc_setup_interface()
2442 marvell_nand->ndtr0 |= in marvell_nfc_setup_interface()
2447 marvell_nand->ndtr1 |= in marvell_nfc_setup_interface()
2459 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nand_attach_chip()
2460 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(nfc->dev); in marvell_nand_attach_chip()
2463 if (pdata && pdata->flash_bbt) in marvell_nand_attach_chip()
2464 chip->bbt_options |= NAND_BBT_USE_FLASH; in marvell_nand_attach_chip()
2466 if (chip->bbt_options & NAND_BBT_USE_FLASH) { in marvell_nand_attach_chip()
2468 * We'll use a bad block table stored in-flash and don't in marvell_nand_attach_chip()
2471 chip->bbt_options |= NAND_BBT_NO_OOB_BBM; in marvell_nand_attach_chip()
2472 chip->bbt_td = &bbt_main_descr; in marvell_nand_attach_chip()
2473 chip->bbt_md = &bbt_mirror_descr; in marvell_nand_attach_chip()
2476 /* Save the chip-specific fields of NDCR */ in marvell_nand_attach_chip()
2477 marvell_nand->ndcr = NDCR_PAGE_SZ(mtd->writesize); in marvell_nand_attach_chip()
2478 if (chip->options & NAND_BUSWIDTH_16) in marvell_nand_attach_chip()
2479 marvell_nand->ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C; in marvell_nand_attach_chip()
2485 if (mtd->writesize <= 512) { in marvell_nand_attach_chip()
2486 marvell_nand->addr_cyc = 1; in marvell_nand_attach_chip()
2488 marvell_nand->addr_cyc = 2; in marvell_nand_attach_chip()
2489 marvell_nand->ndcr |= NDCR_RA_START; in marvell_nand_attach_chip()
2500 if (chip->options & NAND_ROW_ADDR_3) in marvell_nand_attach_chip()
2501 marvell_nand->addr_cyc += 3; in marvell_nand_attach_chip()
2503 marvell_nand->addr_cyc += 2; in marvell_nand_attach_chip()
2506 chip->ecc.size = pdata->ecc_step_size; in marvell_nand_attach_chip()
2507 chip->ecc.strength = pdata->ecc_strength; in marvell_nand_attach_chip()
2510 ret = marvell_nand_ecc_init(mtd, &chip->ecc); in marvell_nand_attach_chip()
2512 dev_err(nfc->dev, "ECC init failed: %d\n", ret); in marvell_nand_attach_chip()
2516 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) { in marvell_nand_attach_chip()
2523 chip->options |= NAND_NO_SUBPAGE_WRITE; in marvell_nand_attach_chip()
2526 if (pdata || nfc->caps->legacy_of_bindings) { in marvell_nand_attach_chip()
2532 mtd->name = "pxa3xx_nand-0"; in marvell_nand_attach_chip()
2533 } else if (!mtd->name) { in marvell_nand_attach_chip()
2537 * should define the following property in your NAND node, ie: in marvell_nand_attach_chip()
2539 * label = "main-storage"; in marvell_nand_attach_chip()
2541 * This way, mtd->name will be set by the core when in marvell_nand_attach_chip()
2544 mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL, in marvell_nand_attach_chip()
2545 "%s:nand.%d", dev_name(nfc->dev), in marvell_nand_attach_chip()
2546 marvell_nand->sels[0].cs); in marvell_nand_attach_chip()
2547 if (!mtd->name) { in marvell_nand_attach_chip()
2548 dev_err(nfc->dev, "Failed to allocate mtd->name\n"); in marvell_nand_attach_chip()
2549 return -ENOMEM; in marvell_nand_attach_chip()
2573 * The legacy "num-cs" property indicates the number of CS on the only in marvell_nand_chip_init()
2577 * When not using legacy bindings, a couple of "reg" and "nand-rb" in marvell_nand_chip_init()
2579 * "reg" points to the CS lines and "nand-rb" to the RB line. in marvell_nand_chip_init()
2581 if (pdata || nfc->caps->legacy_of_bindings) { in marvell_nand_chip_init()
2587 return -EINVAL; in marvell_nand_chip_init()
2591 /* Alloc the nand chip structure */ in marvell_nand_chip_init()
2597 return -ENOMEM; in marvell_nand_chip_init()
2600 marvell_nand->nsels = nsels; in marvell_nand_chip_init()
2601 marvell_nand->selected_die = -1; in marvell_nand_chip_init()
2604 if (pdata || nfc->caps->legacy_of_bindings) { in marvell_nand_chip_init()
2620 if (cs >= nfc->caps->max_cs_nb) { in marvell_nand_chip_init()
2622 cs, nfc->caps->max_cs_nb); in marvell_nand_chip_init()
2623 return -EINVAL; in marvell_nand_chip_init()
2626 if (test_and_set_bit(cs, &nfc->assigned_cs)) { in marvell_nand_chip_init()
2628 return -EINVAL; in marvell_nand_chip_init()
2639 marvell_nand->sels[i].cs = cs; in marvell_nand_chip_init()
2643 marvell_nand->sels[i].ndcb0_csel = 0; in marvell_nand_chip_init()
2647 marvell_nand->sels[i].ndcb0_csel = NDCB0_CSEL; in marvell_nand_chip_init()
2650 return -EINVAL; in marvell_nand_chip_init()
2654 if (pdata || nfc->caps->legacy_of_bindings) { in marvell_nand_chip_init()
2658 ret = of_property_read_u32_index(np, "nand-rb", i, in marvell_nand_chip_init()
2668 if (rb >= nfc->caps->max_rb_nb) { in marvell_nand_chip_init()
2670 rb, nfc->caps->max_rb_nb); in marvell_nand_chip_init()
2671 return -EINVAL; in marvell_nand_chip_init()
2674 marvell_nand->sels[i].rb = rb; in marvell_nand_chip_init()
2677 chip = &marvell_nand->chip; in marvell_nand_chip_init()
2678 chip->controller = &nfc->controller; in marvell_nand_chip_init()
2681 if (of_property_read_bool(np, "marvell,nand-keep-config")) in marvell_nand_chip_init()
2682 chip->options |= NAND_KEEP_TIMINGS; in marvell_nand_chip_init()
2685 mtd->dev.parent = dev; in marvell_nand_chip_init()
2689 * ->setup_interface() is called. in marvell_nand_chip_init()
2691 marvell_nand->ndtr0 = readl_relaxed(nfc->regs + NDTR0); in marvell_nand_chip_init()
2692 marvell_nand->ndtr1 = readl_relaxed(nfc->regs + NDTR1); in marvell_nand_chip_init()
2694 chip->options |= NAND_BUSWIDTH_AUTO; in marvell_nand_chip_init()
2696 ret = nand_scan(chip, marvell_nand->nsels); in marvell_nand_chip_init()
2698 dev_err(dev, "could not scan the nand chip\n"); in marvell_nand_chip_init()
2704 ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts); in marvell_nand_chip_init()
2713 list_add_tail(&marvell_nand->node, &nfc->chips); in marvell_nand_chip_init()
2724 list_for_each_entry_safe(entry, temp, &nfc->chips, node) { in marvell_nand_chips_cleanup()
2725 chip = &entry->chip; in marvell_nand_chips_cleanup()
2729 list_del(&entry->node); in marvell_nand_chips_cleanup()
2735 struct device_node *np = dev->of_node; in marvell_nand_chips_init()
2737 int max_cs = nfc->caps->max_cs_nb; in marvell_nand_chips_init()
2747 dev_err(dev, "too many NAND chips: %d (max = %d CS)\n", nchips, in marvell_nand_chips_init()
2749 return -EINVAL; in marvell_nand_chips_init()
2753 * Legacy bindings do not use child nodes to exhibit NAND chip in marvell_nand_chips_init()
2754 * properties and layout. Instead, NAND properties are mixed with the in marvell_nand_chips_init()
2756 * NAND controller node. in marvell_nand_chips_init()
2758 if (nfc->caps->legacy_of_bindings) { in marvell_nand_chips_init()
2781 struct platform_device *pdev = container_of(nfc->dev, in marvell_nfc_init_dma()
2789 dev_warn(nfc->dev, in marvell_nfc_init_dma()
2791 return -ENOTSUPP; in marvell_nfc_init_dma()
2794 ret = dma_set_mask_and_coherent(nfc->dev, DMA_BIT_MASK(32)); in marvell_nfc_init_dma()
2798 nfc->dma_chan = dma_request_chan(nfc->dev, "data"); in marvell_nfc_init_dma()
2799 if (IS_ERR(nfc->dma_chan)) { in marvell_nfc_init_dma()
2800 ret = PTR_ERR(nfc->dma_chan); in marvell_nfc_init_dma()
2801 nfc->dma_chan = NULL; in marvell_nfc_init_dma()
2802 return dev_err_probe(nfc->dev, ret, "DMA channel request failed\n"); in marvell_nfc_init_dma()
2807 ret = -ENXIO; in marvell_nfc_init_dma()
2813 config.src_addr = r->start + NDDB; in marvell_nfc_init_dma()
2814 config.dst_addr = r->start + NDDB; in marvell_nfc_init_dma()
2817 ret = dmaengine_slave_config(nfc->dma_chan, &config); in marvell_nfc_init_dma()
2819 dev_err(nfc->dev, "Failed to configure DMA channel\n"); in marvell_nfc_init_dma()
2829 nfc->dma_buf = kmalloc(MAX_CHUNK_SIZE, GFP_KERNEL | GFP_DMA); in marvell_nfc_init_dma()
2830 if (!nfc->dma_buf) { in marvell_nfc_init_dma()
2831 ret = -ENOMEM; in marvell_nfc_init_dma()
2835 nfc->use_dma = true; in marvell_nfc_init_dma()
2840 dma_release_channel(nfc->dma_chan); in marvell_nfc_init_dma()
2841 nfc->dma_chan = NULL; in marvell_nfc_init_dma()
2856 NDCR_RD_ID_CNT(NFCV1_READID_LEN), nfc->regs + NDCR); in marvell_nfc_reset()
2857 writel_relaxed(0xFFFFFFFF, nfc->regs + NDSR); in marvell_nfc_reset()
2858 writel_relaxed(0, nfc->regs + NDECCCTRL); in marvell_nfc_reset()
2863 struct device_node *np = nfc->dev->of_node; in marvell_nfc_init()
2866 * Some SoCs like A7k/A8k need to enable manually the NAND in marvell_nfc_init()
2871 if (nfc->caps->need_system_controller) { in marvell_nfc_init()
2874 "marvell,system-controller"); in marvell_nfc_init()
2895 if (!nfc->caps->is_nfcv2) in marvell_nfc_init()
2905 struct device *dev = &pdev->dev; in marvell_nfc_probe()
2910 nfc = devm_kzalloc(&pdev->dev, sizeof(struct marvell_nfc), in marvell_nfc_probe()
2913 return -ENOMEM; in marvell_nfc_probe()
2915 nfc->dev = dev; in marvell_nfc_probe()
2916 nand_controller_init(&nfc->controller); in marvell_nfc_probe()
2917 nfc->controller.ops = &marvell_nand_controller_ops; in marvell_nfc_probe()
2918 INIT_LIST_HEAD(&nfc->chips); in marvell_nfc_probe()
2920 nfc->regs = devm_platform_ioremap_resource(pdev, 0); in marvell_nfc_probe()
2921 if (IS_ERR(nfc->regs)) in marvell_nfc_probe()
2922 return PTR_ERR(nfc->regs); in marvell_nfc_probe()
2928 nfc->core_clk = devm_clk_get(&pdev->dev, "core"); in marvell_nfc_probe()
2931 if (nfc->core_clk == ERR_PTR(-ENOENT)) in marvell_nfc_probe()
2932 nfc->core_clk = devm_clk_get(&pdev->dev, NULL); in marvell_nfc_probe()
2934 if (IS_ERR(nfc->core_clk)) in marvell_nfc_probe()
2935 return PTR_ERR(nfc->core_clk); in marvell_nfc_probe()
2937 ret = clk_prepare_enable(nfc->core_clk); in marvell_nfc_probe()
2941 nfc->reg_clk = devm_clk_get(&pdev->dev, "reg"); in marvell_nfc_probe()
2942 if (IS_ERR(nfc->reg_clk)) { in marvell_nfc_probe()
2943 if (PTR_ERR(nfc->reg_clk) != -ENOENT) { in marvell_nfc_probe()
2944 ret = PTR_ERR(nfc->reg_clk); in marvell_nfc_probe()
2948 nfc->reg_clk = NULL; in marvell_nfc_probe()
2951 ret = clk_prepare_enable(nfc->reg_clk); in marvell_nfc_probe()
2958 0, "marvell-nfc", nfc); in marvell_nfc_probe()
2962 /* Get NAND controller capabilities */ in marvell_nfc_probe()
2963 if (pdev->id_entry) in marvell_nfc_probe()
2964 nfc->caps = (void *)pdev->id_entry->driver_data; in marvell_nfc_probe()
2966 nfc->caps = of_device_get_match_data(&pdev->dev); in marvell_nfc_probe()
2968 if (!nfc->caps) { in marvell_nfc_probe()
2970 ret = -EINVAL; in marvell_nfc_probe()
2988 if (nfc->use_dma) in marvell_nfc_probe()
2989 dma_release_channel(nfc->dma_chan); in marvell_nfc_probe()
2991 clk_disable_unprepare(nfc->reg_clk); in marvell_nfc_probe()
2993 clk_disable_unprepare(nfc->core_clk); in marvell_nfc_probe()
3004 if (nfc->use_dma) { in marvell_nfc_remove()
3005 dmaengine_terminate_all(nfc->dma_chan); in marvell_nfc_remove()
3006 dma_release_channel(nfc->dma_chan); in marvell_nfc_remove()
3009 clk_disable_unprepare(nfc->reg_clk); in marvell_nfc_remove()
3010 clk_disable_unprepare(nfc->core_clk); in marvell_nfc_remove()
3020 list_for_each_entry(chip, &nfc->chips, node) in marvell_nfc_suspend()
3021 marvell_nfc_wait_ndrun(&chip->chip); in marvell_nfc_suspend()
3023 clk_disable_unprepare(nfc->reg_clk); in marvell_nfc_suspend()
3024 clk_disable_unprepare(nfc->core_clk); in marvell_nfc_suspend()
3034 ret = clk_prepare_enable(nfc->core_clk); in marvell_nfc_resume()
3038 ret = clk_prepare_enable(nfc->reg_clk); in marvell_nfc_resume()
3040 clk_disable_unprepare(nfc->core_clk); in marvell_nfc_resume()
3045 * Reset nfc->selected_chip so the next command will cause the timing in marvell_nfc_resume()
3048 nfc->selected_chip = NULL; in marvell_nfc_resume()
3103 .name = "pxa3xx-nand",
3112 .compatible = "marvell,armada-8k-nand-controller",
3116 .compatible = "marvell,armada370-nand-controller",
3120 .compatible = "marvell,pxa3xx-nand-controller",
3125 .compatible = "marvell,armada-8k-nand",
3129 .compatible = "marvell,armada370-nand",
3133 .compatible = "marvell,pxa3xx-nand",
3142 .name = "marvell-nfc",
3153 MODULE_DESCRIPTION("Marvell NAND controller driver");