| /Linux-v6.1/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/ |
| D | metrics.json | 74 "PublicDescription": "Idle by itlb miss L3 topdown metric",
75 "BriefDescription": "Idle by itlb miss L3 topdown metric",
81 "PublicDescription": "Idle by icache miss L3 topdown metric",
82 "BriefDescription": "Idle by icache miss L3 topdown metric",
88 "PublicDescription": "BP misp flush L3 topdown metric",
89 "BriefDescription": "BP misp flush L3 topdown metric",
95 "PublicDescription": "OOO flush L3 topdown metric",
96 "BriefDescription": "OOO flush L3 topdown metric",
102 "PublicDescription": "Static predictor flush L3 topdown metric",
103 "BriefDescription": "Static predictor flush L3 topdown metric",
[all …]
|
| /Linux-v6.1/drivers/bus/ |
| D | omap_l3_noc.c | 3 * OMAP L3 Interconnect error handling driver
23 * @l3: pointer to l3 struct
35 * 1) Custom errors in L3 :
37 * 2) Standard L3 error:
39 * L3 tries to access target while it is idle
50 static int l3_handle_target(struct omap_l3 *l3, void __iomem *base, in l3_handle_target() argument
114 l3->mst_addr_mask) >> __ffs(l3->mst_addr_mask); in l3_handle_target()
116 for (k = 0, master = l3->l3_masters; k < l3->num_masters; in l3_handle_target()
134 "%s:L3 %s Error: MASTER %s TARGET %s (%s)%s%s\n", in l3_handle_target()
135 dev_name(l3->dev), in l3_handle_target()
[all …]
|
| D | omap_l3_smx.c | 3 * OMAP3XXX L3 Interconnect Driver
130 * @l3: struct omap3_l3 *
140 static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3, in omap3_l3_block_irq() argument
159 struct omap3_l3 *l3 = _l3; in omap3_l3_app_irq() local
168 int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR; in omap3_l3_app_irq()
170 status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0); in omap3_l3_app_irq()
179 status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_1); in omap3_l3_app_irq()
186 base = l3->rt + omap3_l3_bases[int_type][err_source]; in omap3_l3_app_irq()
190 ret |= omap3_l3_block_irq(l3, error, error_addr); in omap3_l3_app_irq()
207 .compatible = "ti,omap3-l3-smx",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/sandybridge/ |
| D | uncore-cache.json | 3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
8 … "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
13 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
18 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
23 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
28 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
33 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
38 … "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
43 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-s…
48 …"PublicDescription": "L3 Lookup external snoop request that access cache and found line in E or S-…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/haswell/ |
| D | uncore-cache.json | 3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
8 … "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
13 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
18 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
23 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
28 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
33 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
38 … "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
43 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-s…
48 …"PublicDescription": "L3 Lookup external snoop request that access cache and found line in E or S-…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/ivybridge/ |
| D | uncore-cache.json | 3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
8 … "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
13 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
18 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
23 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
28 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
33 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
38 … "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
43 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-s…
48 …"PublicDescription": "L3 Lookup external snoop request that access cache and found line in E or S-…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/broadwell/ |
| D | uncore-cache.json | 3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state",
8 … "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
13 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
18 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
23 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
28 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
33 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
38 … "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
43 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
48 … "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/skylake/ |
| D | uncore-cache.json | 3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state",
8 … "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
13 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
18 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
23 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
28 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
33 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
38 … "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
43 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
48 … "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/elkhartlake/ |
| D | memory.json | 36 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
47 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
58 …": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",
69 …": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",
80 …d instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
91 …d instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
102 …are prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
113 …are prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
146 …d software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
157 …d software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
[all …]
|
| D | cache.json | 91 …struction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, …
103 …struction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, …
221 …"BriefDescription": "Counts the number of load uops retired that hit in the L3 cache, in which a s…
281 "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.",
380 "BriefDescription": "Counts all code reads that were supplied by the L3 cache.",
391 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se…
402 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se…
413 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se…
424 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se…
435 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where no snoop was n…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/snowridgex/ |
| D | memory.json | 36 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
47 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
58 …": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",
69 …": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",
80 …d instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
91 …d instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
102 …are prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
113 …are prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
146 …d software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
157 …d software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
[all …]
|
| D | cache.json | 91 …struction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, …
103 …struction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, …
221 …"BriefDescription": "Counts the number of load uops retired that hit in the L3 cache, in which a s…
281 "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.",
380 "BriefDescription": "Counts all code reads that were supplied by the L3 cache.",
391 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se…
402 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se…
413 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se…
424 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se…
435 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where no snoop was n…
[all …]
|
| /Linux-v6.1/arch/sparc/kernel/ |
| D | head_64.S | 175 mov 1, %l3
176 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
177 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
199 mov 4, %l3
200 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
201 mov 1, %l3
202 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
206 mov 64, %l3
207 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
214 mov (1b - prom_boot_mapped_pc), %l3
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/interconnect/ |
| D | qcom,osm-l3.yaml | 4 $id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml#
7 title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider
13 L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.
14 The OSM L3 interconnect provider aggregates the L3 bandwidth requests
20 - qcom,sc7180-osm-l3
21 - qcom,sc7280-epss-l3
22 - qcom,sc8180x-osm-l3
23 - qcom,sdm845-osm-l3
24 - qcom,sm8150-osm-l3
25 - qcom,sm8250-epss-l3
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/powerpc/power8/ |
| D | cache.json | 5 …s data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node …
6 …s data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node …
11 …r's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node …
12 …r's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node …
65 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand …
66 …"PublicDescription": "The processor's data cache was reloaded from local core's L3 due to either o…
71 "BriefDescription": "Demand LD - L3 Miss (not L2 hit and not L3 hit)",
77 …ssor's data cache was reloaded from a location other than the local core's L3 due to a demand load…
78 …ssor's data cache was reloaded from a location other than the local core's L3 due to either only d…
83 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch co…
[all …]
|
| D | metrics.json | 207 …escription": "Cycles stalled by GCT empty due to Icache misses that resolve in the local L2 or L3",
255 …"BriefDescription": "Cycles stalled by D-Cache Misses that resolved in the local L2 or L3, where t…
261 "BriefDescription": "Cycles stalled by D-Cache Misses that resolved in the local L2 or L3",
267 …"BriefDescription": "Cycles stalled by D-Cache Misses that resolved in the local L2 or L3, where t…
456 "BriefDescription": "% of DL1 Reloads from Distant L2 or L3 (Modified) per Inst",
462 "BriefDescription": "% of DL1 Reloads from Distant L2 or L3 (Shared) per Inst",
522 "BriefDescription": "% of DL1 reloads from Private L3 M state, other core per Inst",
528 "BriefDescription": "% of DL1 reloads from Private L3 S tate, other core per Inst",
534 …"BriefDescription": "Percentage of L3 load hits per instruction where the load collided with a pen…
540 "BriefDescription": "% of DL1 reloads from L3 per Inst",
[all …]
|
| D | frontend.json | 89 …uction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node …
90 …uction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node …
95 …truction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node …
96 …truction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node …
149 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an…
150 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 due to e…
156 "PublicDescription": "Inst from L3 miss"
161 …Instruction cache was reloaded from a location other than the local core's L3 due to a instruction…
162 …Instruction cache was reloaded from a location other than the local core's L3 due to either an ins…
167 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 with disp…
[all …]
|
| D | marked.json | 35 …s data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node …
41 …ation in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node …
47 …r's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node …
53 …uration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node …
155 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a marked …
161 …ssor's data cache was reloaded from a location other than the local core's L3 due to a marked load…
167 … "Duration in cycles to reload from a location other than the local core's L3 due to a marked load…
173 "BriefDescription": "Duration in cycles to reload from local core's L3 due to a marked load",
179 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch co…
185 …"BriefDescription": "Duration in cycles to reload from local core's L3 with dispatch conflict due …
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/arm/omap/ |
| D | l3-noc.txt | 1 * TI - L3 Network On Chip (NoC)
7 - compatible : Should be "ti,omap3-l3-smx" for OMAP3 family
8 Should be "ti,omap4-l3-noc" for OMAP4 family
9 Should be "ti,omap5-l3-noc" for OMAP5 family
10 Should be "ti,dra7-l3-noc" for DRA7 family
11 Should be "ti,am4372-l3-noc" for AM43 family
12 - reg: Contains L3 register address range for each noc domain.
18 compatible = "ti,omap4-l3-noc", "simple-bus";
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | memory.json | 3 "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
13 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
231 "BriefDescription": "Demand Data Read requests who miss L3 cache",
236 "PublicDescription": "Demand Data Read requests who miss L3 cache.",
241 …"BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the sup…
251 … "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ …
260 …"BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the su…
270 "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3.",
282 …"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified dat…
294 …"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared …
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/powerpc/power9/ |
| D | other.json | 35 "BriefDescription": "L3 initiated LCO received retry on port 2 (can try 4 times)"
45 …ssor's data cache was reloaded from a location other than the local core's L3 due to a marked load"
50 …try was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due…
120 …"BriefDescription": "L3 TM CAM is full when a L2 castout of TM_SC line occurs. Line is pushed to …
160 "BriefDescription": "L3 PF from Off chip memory"
190 …"BriefDescription": "TM snoop that is a store hits line in L3 in T, Tn or Te state (shared modifie…
205 …uration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due…
235 … "BriefDescription": "Core TM load hits line in L3 in TM_SC state and causes it to be invalidated"
245 "BriefDescription": "L3 PF sent with nodal scope port 1, counts even retried requests"
260 "BriefDescription": "L3 CO received retry port 3 (memory only), every retry counted"
[all …]
|
| D | marked.json | 10 …ory Entry was reloaded to a level 1 page walk cache from beyond the core's L3 data cache. The sour…
20 …ble Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due…
50 …Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache. This imp…
70 …Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due…
85 …Instruction cache was reloaded from a location other than the local core's L3 due to a instruction…
95 …try was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due…
100 …Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due…
110 … "Duration in cycles to reload from a location other than the local core's L3 due to a marked load"
180 …ocessor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due…
185 …essor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due…
[all …]
|
| D | metrics.json | 80 …iefDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)",
86 …"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a confl…
92 …"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 without conf…
98 "BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3",
104 "BriefDescription": "Completion stall due to cache miss resolving missed the L3",
271 …n Completion Table empty for this thread due to icache misses that were sourced from the local L3",
277 …r this thread due to icache misses that were sourced from beyond the local L3. The source could be…
601 "BriefDescription": "% of DL1 Reloads from Distant L2 or L3 (Modified) per Inst",
607 "BriefDescription": "% of DL1 Reloads from Distant L2 or L3 (Shared) per Inst",
643 "BriefDescription": "% of DL1 reloads from Private L3 M state, other core per Inst",
[all …]
|
| /Linux-v6.1/tools/testing/selftests/drivers/net/netdevsim/ |
| D | hw_stats_l3.sh | 242 reporting_test l3
291 fail_next_test l3
318 local pkts=$(get_hwstat dummy1 l3 rx.packets)
324 local pkts=$(get_hwstat dummy1 l3 rx.packets)
333 local pkts=$(get_hwstat dummy1 l3 rx.packets)
345 local pkts=$(get_hwstat dummy1 l3 rx.packets)
356 counter_test l3
365 nsim_hwstats_enable 1 dummy1 l3
366 nsim_hwstats_enable 2 dummy1 l3
367 nsim_hwstats_enable 3 dummy1 l3
[all …]
|
| /Linux-v6.1/drivers/gpu/drm/i915/gt/ |
| D | intel_mocs.c | 69 /* L3 caching options */
98 * PTE and those platforms except TGL/RKL will be initialized L3 WB to
112 * indices have been set to L3 WB. These reserved entries should never
115 * For TGL/RKL, all the unspecified MOCS indexes are mapped to L3 UC.
133 * - used by the L3 for all of its evictions.
136 * - used to force L3 uncachable cycles.
137 * Thus it is expected to make the surface L3 uncacheable.
154 /* Base - L3 + LLC */ \
162 /* Base - L3 */ \
174 /* Age 0 - L3 + LLC */ \
[all …]
|
