Lines Matching full:l3
69 /* L3 caching options */
98 * PTE and those platforms except TGL/RKL will be initialized L3 WB to
112 * indices have been set to L3 WB. These reserved entries should never
115 * For TGL/RKL, all the unspecified MOCS indexes are mapped to L3 UC.
133 * - used by the L3 for all of its evictions.
136 * - used to force L3 uncachable cycles.
137 * Thus it is expected to make the surface L3 uncacheable.
154 /* Base - L3 + LLC */ \
162 /* Base - L3 */ \
174 /* Age 0 - L3 + LLC */ \
182 /* Age: Don't Chg. - L3 + LLC */ \
190 /* No AOM - L3 + LLC */ \
198 /* No AOM; Age 0 - L3 + LLC */ \
206 /* No AOM; Age:DC - L3 + LLC */ \
214 /* Bypass LLC - L3 (Read-Only) (EHL+) */ \
218 /* Self-Snoop - L3 + LLC */ \
222 /* Skip Caching - L3 + LLC(12.5%) */ \
226 /* Skip Caching - L3 + LLC(25%) */ \
230 /* Skip Caching - L3 + LLC(50%) */ \
234 /* Skip Caching - L3 + LLC(75%) */ \
238 /* Skip Caching - L3 + LLC(87.5%) */ \
254 * Reserved and unspecified MOCS indices have been set to (L3 + LCC).
266 /* Implicitly enable L1 - HDC:L1 + L3 + LLC */
270 /* Implicitly enable L1 - HDC:L1 + L3 */
297 /* Base - L3 + LeCC:PAT (Deprecated) */
309 /* WB - L3 */
311 /* WB - L3 50% */
313 /* WB - L3 25% */
315 /* WB - L3 12.5% */
318 /* HDC:L1 + L3 */
332 /* Implicitly enable L1 - HDC:L1 + L3 + LLC */
336 /* Implicitly enable L1 - HDC:L1 + L3 */
362 /* UC - Coherent; GO:L3 */
368 /* UC - Non-Coherent; GO:L3 */
384 /* UC - Coherent; GO:L3 */