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/Linux-v6.1/drivers/isdn/mISDN/
Dlayer2.c92 struct layer2 *l2 = fi->userdata; in l2m_debug() local
104 printk(KERN_DEBUG "%s l2 (sapi %d tei %d): %pV\n", in l2m_debug()
105 mISDNDevName4ch(&l2->ch), l2->sapi, l2->tei, &vaf); in l2m_debug()
111 l2headersize(struct layer2 *l2, int ui) in l2headersize() argument
113 return ((test_bit(FLG_MOD128, &l2->flag) && (!ui)) ? 2 : 1) + in l2headersize()
114 (test_bit(FLG_LAPD, &l2->flag) ? 2 : 1); in l2headersize()
118 l2addrsize(struct layer2 *l2) in l2addrsize() argument
120 return test_bit(FLG_LAPD, &l2->flag) ? 2 : 1; in l2addrsize()
124 l2_newid(struct layer2 *l2) in l2_newid() argument
128 id = l2->next_id++; in l2_newid()
[all …]
Dtei.c109 struct layer2 *l2; in da_deactivate() local
113 list_for_each_entry(l2, &mgr->layer2, list) { in da_deactivate()
114 if (l2->l2m.state > ST_L2_4) { in da_deactivate()
146 struct layer2 *l2; in da_timer() local
151 list_for_each_entry(l2, &mgr->layer2, list) { in da_timer()
152 if (l2->l2m.state > ST_L2_4) { in da_timer()
234 tm->l2->sapi, tm->l2->tei, &vaf); in tei_debug()
246 struct layer2 *l2; in get_free_id() local
248 list_for_each_entry(l2, &mgr->layer2, list) { in get_free_id()
249 if (l2->ch.nr > 63) { in get_free_id()
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/Linux-v6.1/Documentation/devicetree/bindings/powerpc/fsl/
Dl2cache.txt1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
9 "fsl,b4420-l2-cache-controller"
10 "fsl,b4860-l2-cache-controller"
11 "fsl,bsc9131-l2-cache-controller"
12 "fsl,bsc9132-l2-cache-controller"
13 "fsl,c293-l2-cache-controller"
14 "fsl,mpc8536-l2-cache-controller"
15 "fsl,mpc8540-l2-cache-controller"
16 "fsl,mpc8541-l2-cache-controller"
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/Linux-v6.1/tools/perf/pmu-events/arch/x86/amdzen1/
Dcache.json15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
30 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs."
58 …"BriefDescription": "IC line invalidated due to L2 invalidating probe (external or LS). The number…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
87 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
93 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
99 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
105 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
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Drecommended.json17 "BriefDescription": "All L2 Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35 "BriefDescription": "L2 Cache Accesses from L2 HWPF",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 HWPF",
65 "BriefDescription": "All L2 Cache Hits",
72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
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/Linux-v6.1/drivers/memory/
Dbt1-l2-ctl.c8 * Baikal-T1 CM2 L2-cache Control Block driver.
38 * struct l2_ctl - Baikal-T1 L2 Control block private data.
49 * enum l2_ctl_stall - Baikal-T1 L2-cache-RAM stall identifier.
61 * struct l2_ctl_device_attribute - Baikal-T1 L2-cache device attribute.
63 * @id: L2-cache stall field identifier.
77 static int l2_ctl_get_latency(struct l2_ctl *l2, enum l2_ctl_stall id, u32 *val) in l2_ctl_get_latency() argument
82 ret = regmap_read(l2->sys_regs, L2_CTL_REG, &data); in l2_ctl_get_latency()
103 static int l2_ctl_set_latency(struct l2_ctl *l2, enum l2_ctl_stall id, u32 val) in l2_ctl_set_latency() argument
130 ret = regmap_update_bits(l2->sys_regs, L2_CTL_REG, mask, data); in l2_ctl_set_latency()
134 return regmap_read_poll_timeout(l2->sys_regs, L2_CTL_REG, data, in l2_ctl_set_latency()
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/Linux-v6.1/tools/perf/pmu-events/arch/x86/amdzen2/
Dcache.json5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
Drecommended.json17 "BriefDescription": "All L2 Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35 "BriefDescription": "L2 Cache Accesses from L2 HWPF",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 HWPF",
65 "BriefDescription": "All L2 Cache Hits",
72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
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/Linux-v6.1/tools/perf/pmu-events/arch/x86/amdzen3/
Dcache.json5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
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/Linux-v6.1/tools/perf/pmu-events/arch/x86/bonnell/
Dcache.json59 "BriefDescription": "Cycles L2 address bus is in use.",
107 "BriefDescription": "Cycles the L2 cache data bus is busy.",
115 "BriefDescription": "Cycles the L2 transfers data to the core.",
123 "BriefDescription": "L2 cacheable instruction fetch requests",
131 "BriefDescription": "L2 cacheable instruction fetch requests",
139 "BriefDescription": "L2 cacheable instruction fetch requests",
147 "BriefDescription": "L2 cacheable instruction fetch requests",
155 "BriefDescription": "L2 cacheable instruction fetch requests",
163 "BriefDescription": "L2 cache reads",
171 "BriefDescription": "L2 cache reads",
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/Linux-v6.1/tools/perf/pmu-events/arch/x86/goldmont/
Dcache.json37 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
41 "BriefDescription": "L2 cache request misses",
46 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
51 "BriefDescription": "L2 cache requests",
56 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
68 … ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit…
109 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
116 "PublicDescription": "Counts load uops retired that hit in the L2 cache.",
121 "BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
128 "PublicDescription": "Counts load uops retired that miss in the L2 cache.",
[all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/goldmontplus/
Dcache.json45 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
49 "BriefDescription": "L2 cache request misses",
56 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
61 "BriefDescription": "L2 cache requests",
68 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
81 … ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit…
125 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
133 "PublicDescription": "Counts load uops retired that hit in the L2 cache.",
138 "BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
146 "PublicDescription": "Counts load uops retired that miss in the L2 cache.",
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/Linux-v6.1/tools/perf/pmu-events/arch/x86/knightslanding/
Dcache.json3 … number of MEC requests that were not accepted into the L2Q because of any L2 queue reject condit…
19 "BriefDescription": "Counts the number of L2 cache misses",
27 "BriefDescription": "Counts the total number of L2 cache references.",
35 … a cache line (cacheable requests) exlcuding SW prefetches filling only to L2 cache and L1 evictio…
79 "BriefDescription": "Counts the number of load micro-ops retired that hit in the L2",
89 "BriefDescription": "Counts the number of load micro-ops retired that miss in the L2",
126 … forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Vali…
137 …rwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid …
148 … data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
159 …or reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
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/Linux-v6.1/tools/perf/pmu-events/arch/x86/silvermont/
Dcache.json7 … eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests …
20 … "BriefDescription": "Counts the number of request from the L2 that were not accepted into the XQ",
24 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the I…
28 "BriefDescription": "L2 cache request misses",
32 …licDescription": "This event counts the total number of L2 cache references and the number of L2 c…
37 "BriefDescription": "L2 cache requests from this core",
41 …his event counts requests originating from the core that references a cache line in the L2 cache.",
83 "BriefDescription": "Loads hit L2",
88 "PublicDescription": "This event counts the number of load ops retired that hit in the L2.",
93 "BriefDescription": "Loads missed L2",
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/Linux-v6.1/tools/perf/pmu-events/arch/x86/broadwellde/
Dcache.json55 "BriefDescription": "Not rejected writebacks that hit L2 cache",
60 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
65 "BriefDescription": "L2 cache lines filling L2",
70 …"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does…
75 "BriefDescription": "L2 cache lines in E state filling L2",
80 …licDescription": "This event counts the number of L2 cache lines in the Exclusive state filling th…
85 "BriefDescription": "L2 cache lines in I state filling L2",
90 …licDescription": "This event counts the number of L2 cache lines in the Invalidate state filling t…
95 "BriefDescription": "L2 cache lines in S state filling L2",
100 …ublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the…
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/Linux-v6.1/tools/perf/pmu-events/arch/x86/haswell/
Dcache.json63 "BriefDescription": "Not rejected writebacks that hit L2 cache",
68 "PublicDescription": "Not rejected writebacks that hit L2 cache.",
73 "BriefDescription": "L2 cache lines filling L2",
78 …event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2…
83 "BriefDescription": "L2 cache lines in E state filling L2",
88 "PublicDescription": "L2 cache lines in E state filling L2.",
93 "BriefDescription": "L2 cache lines in I state filling L2",
98 "PublicDescription": "L2 cache lines in I state filling L2.",
103 "BriefDescription": "L2 cache lines in S state filling L2",
108 "PublicDescription": "L2 cache lines in S state filling L2.",
[all …]
/Linux-v6.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/
Dcache.json102 …L2 cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this ev…
105 …L2 cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this ev…
114 …: "L2 cache write streaming mode. This event counts for each cycle where the core is in write stre…
117 …: "L2 cache write streaming mode. This event counts for each cycle where the core is in write stre…
144 … "PublicDescription": "L2 TLB walk cache access. This event does not count if the MMU is disabled",
147 … "BriefDescription": "L2 TLB walk cache access. This event does not count if the MMU is disabled"
150 … "PublicDescription": "L2 TLB walk cache refill. This event does not count if the MMU is disabled",
153 … "BriefDescription": "L2 TLB walk cache refill. This event does not count if the MMU is disabled"
156 …"PublicDescription": "L2 TLB IPA cache access. This event counts on each access to the IPA cache. …
159 …"BriefDescription": "L2 TLB IPA cache access. This event counts on each access to the IPA cache. I…
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/memory-controllers/
Dbaikal,bt1-l2-ctl.yaml5 $id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-l2-ctl.yaml#
8 title: Baikal-T1 L2-cache Control Block
15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
17 L2-cache controller block is responsible for the tuning. Its DT node is
22 const: baikal,bt1-l2-ctl
27 baikal,l2-ws-latency:
34 baikal,l2-tag-latency:
41 baikal,l2-data-latency:
55 l2@1f04d028 {
56 compatible = "baikal,bt1-l2-ctl";
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/Linux-v6.1/tools/perf/pmu-events/arch/x86/haswellx/
Dcache.json63 "BriefDescription": "Not rejected writebacks that hit L2 cache",
68 "PublicDescription": "Not rejected writebacks that hit L2 cache.",
73 "BriefDescription": "L2 cache lines filling L2",
78 …event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2…
83 "BriefDescription": "L2 cache lines in E state filling L2",
88 "PublicDescription": "L2 cache lines in E state filling L2.",
93 "BriefDescription": "L2 cache lines in I state filling L2",
98 "PublicDescription": "L2 cache lines in I state filling L2.",
103 "BriefDescription": "L2 cache lines in S state filling L2",
108 "PublicDescription": "L2 cache lines in S state filling L2.",
[all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/ivybridge/
Dcache.json56 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
65 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
70 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
75 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
80 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
85 …"BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-reject…
95 "BriefDescription": "L2 cache lines filling L2",
100 "PublicDescription": "L2 cache lines filling L2.",
105 "BriefDescription": "L2 cache lines in E state filling L2",
110 "PublicDescription": "L2 cache lines in E state filling L2.",
[all …]
/Linux-v6.1/tools/perf/pmu-events/arch/powerpc/power8/
Dcache.json5 …essor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different…
6 …essor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different…
11 …ocessor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different…
12 …ocessor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different…
23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand …
24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o…
29 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)",
35 …ssor's data cache was reloaded from a location other than the local core's L2 due to a demand load…
36 …ssor's data cache was reloaded from a location other than the local core's L2 due to either only d…
41 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit st…
[all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/tigerlake/
Dcache.json38 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
44 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re…
72 "BriefDescription": "L2 cache lines filling L2",
78 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover …
83 …riefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache…
89 …scription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache…
94 …on": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache…
100 …": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache…
105 "BriefDescription": "L2 code requests",
111 "PublicDescription": "Counts the total number of L2 code requests.",
[all …]
/Linux-v6.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/
Dcache.json7 …"PublicDescription": "This event counts any refill of the instruction L1 TLB from the L2 TLB. This…
19 …"PublicDescription": "This event counts any refill of the data L1 TLB from the L2 TLB. This includ…
27 …"PublicDescription": "This event counts any write-back of data from the L1 data cache to L2 or L3.…
31 …unts any transaction from L1 which looks up in the L2 cache, and any write-back from the L1 to the…
35 …L2 data cache refill. This event counts any cacheable transaction from L1 which causes data to be …
39 …L2 cache to outside the core. This includes snoops to the L2 which return data, regardless of whet…
43 …ts any full cache line write into the L2 cache which does not cause a linefill, including write-ba…
57 …t cause a linefill, including write-backs from L2 to L3 and full-line writes which do not allocate…
72 …"PublicDescription": "This event counts on anyrefill of the L2 TLB, caused by either an instructio…
74 "BriefDescription": "Attributable L2 data or unified TLB refill"
[all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/broadwellx/
Dcache.json55 "BriefDescription": "Not rejected writebacks that hit L2 cache",
60 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
65 "BriefDescription": "L2 cache lines filling L2",
70 …"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does…
75 "BriefDescription": "L2 cache lines in E state filling L2",
80 …licDescription": "This event counts the number of L2 cache lines in the Exclusive state filling th…
85 "BriefDescription": "L2 cache lines in I state filling L2",
90 …licDescription": "This event counts the number of L2 cache lines in the Invalidate state filling t…
95 "BriefDescription": "L2 cache lines in S state filling L2",
100 …ublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the…
[all …]
/Linux-v6.1/arch/parisc/lib/
Dio.c169 unsigned int l = 0, l2; in insw() local
221 l2 = cpu_to_le16(inw(port)); in insw()
222 *(unsigned short *)p = (l & 0xff) << 8 | (l2 >> 8); in insw()
224 l = l2; in insw()
241 unsigned int l = 0, l2; in insl() local
268 l2 = cpu_to_le32(inl(port)); in insl()
269 *(unsigned int *)p = (l & 0xffff) << 16 | (l2 >> 16); in insl()
271 l = l2; in insl()
285 l2 = cpu_to_le32(inl(port)); in insl()
286 *(unsigned int *)p = (l & 0xff) << 24 | (l2 >> 8); in insl()
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