Lines Matching full:l2
63 "BriefDescription": "Not rejected writebacks that hit L2 cache",
68 "PublicDescription": "Not rejected writebacks that hit L2 cache.",
73 "BriefDescription": "L2 cache lines filling L2",
78 …event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2…
83 "BriefDescription": "L2 cache lines in E state filling L2",
88 "PublicDescription": "L2 cache lines in E state filling L2.",
93 "BriefDescription": "L2 cache lines in I state filling L2",
98 "PublicDescription": "L2 cache lines in I state filling L2.",
103 "BriefDescription": "L2 cache lines in S state filling L2",
108 "PublicDescription": "L2 cache lines in S state filling L2.",
113 "BriefDescription": "Clean L2 cache lines evicted by demand",
118 "PublicDescription": "Clean L2 cache lines evicted by demand.",
123 "BriefDescription": "Dirty L2 cache lines evicted by demand",
128 "PublicDescription": "Dirty L2 cache lines evicted by demand.",
133 "BriefDescription": "L2 code requests",
138 "PublicDescription": "Counts all L2 code requests.",
149 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
154 "BriefDescription": "Demand requests that miss L2 cache",
160 "PublicDescription": "Demand requests that miss L2 cache.",
165 "BriefDescription": "Demand requests to L2 cache",
171 "PublicDescription": "Demand requests to L2 cache.",
176 "BriefDescription": "Requests from L2 hardware prefetchers",
181 "PublicDescription": "Counts all L2 HW prefetcher requests.",
186 "BriefDescription": "RFO requests to L2 cache",
191 "PublicDescription": "Counts all L2 store RFO requests.",
196 "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
201 "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
206 "BriefDescription": "L2 cache misses when fetching instructions",
211 "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
216 "BriefDescription": "Demand Data Read requests that hit L2 cache",
222 …Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache",
227 "BriefDescription": "Demand Data Read miss L2, no rejects",
233 "PublicDescription": "Demand data read requests that missed L2, no rejects.",
238 "BriefDescription": "L2 prefetch requests that hit L2 cache",
243 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
248 "BriefDescription": "L2 prefetch requests that miss L2 cache",
253 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
258 "BriefDescription": "All requests that miss L2 cache",
264 "PublicDescription": "All requests that missed L2.",
269 "BriefDescription": "All L2 requests",
275 "PublicDescription": "All requests to L2 cache.",
280 "BriefDescription": "RFO requests that hit L2 cache",
285 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.",
290 "BriefDescription": "RFO requests that miss L2 cache",
295 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
300 "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
305 "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.",
310 "BriefDescription": "Transactions accessing L2 pipe",
315 "PublicDescription": "Transactions accessing L2 pipe.",
320 "BriefDescription": "L2 cache accesses when fetching instructions",
325 "PublicDescription": "L2 cache accesses when fetching instructions.",
330 "BriefDescription": "Demand Data Read requests that access L2 cache",
335 "PublicDescription": "Demand data read requests that access L2 cache.",
340 "BriefDescription": "L1D writebacks that access L2 cache",
345 "PublicDescription": "L1D writebacks that access L2 cache.",
350 "BriefDescription": "L2 fill requests that access L2 cache",
355 "PublicDescription": "L2 fill requests that access L2 cache.",
360 "BriefDescription": "L2 writebacks that access L2 cache",
365 "PublicDescription": "L2 writebacks that access L2 cache.",
370 "BriefDescription": "RFO requests that access L2 cache",
375 "PublicDescription": "RFO requests that access L2 cache.",
508 "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
520 "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
528 "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.",
975 "BriefDescription": "Counts prefetch (that bring data to L2) data readshit in the L3",
987 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOshit in the L3",