| /Linux-v6.6/drivers/isdn/mISDN/ |
| D | layer1.c | 94 struct layer1 *l1 = fi->userdata; in l1m_debug() local
103 printk(KERN_DEBUG "%s: %pV\n", dev_name(&l1->dch->dev.dev), &vaf); in l1m_debug()
117 struct layer1 *l1 = fi->userdata; in l1_deact_cnf() local
120 if (test_bit(FLG_L1_ACTIVATING, &l1->Flags)) in l1_deact_cnf()
121 l1->dcb(l1->dch, HW_POWERUP_REQ); in l1_deact_cnf()
127 struct layer1 *l1 = fi->userdata; in l1_deact_req_s() local
130 mISDN_FsmRestartTimer(&l1->timerX, 550, EV_TIMER_DEACT, NULL, 2); in l1_deact_req_s()
131 test_and_set_bit(FLG_L1_DEACTTIMER, &l1->Flags); in l1_deact_req_s()
137 struct layer1 *l1 = fi->userdata; in l1_power_up_s() local
139 if (test_bit(FLG_L1_ACTIVATING, &l1->Flags)) { in l1_power_up_s()
[all …]
|
| /Linux-v6.6/Documentation/networking/ |
| D | tls-offload-layers.svg | 1 …l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.82812…
|
| /Linux-v6.6/tools/perf/pmu-events/arch/x86/amdzen4/ |
| D | memory.json | 40 "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 4k pages.",
46 …"BriefDescription": "L1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 1…
52 "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 2M pages.",
58 "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 1G pages.",
64 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pa…
70 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coale…
76 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 2M pa…
82 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 1G pa…
88 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for all p…
94 "BriefDescription": "L1 DTLB misses for all page sizes.",
[all …]
|
| D | recommended.json | 23 "BriefDescription": "L2 cache accesses from L1 instruction cache misses (including prefetch).",
29 "BriefDescription": "L2 cache accesses from L1 data cache misses (including prefetch).",
47 "BriefDescription": "L2 cache misses from L1 instruction cache misses.",
53 "BriefDescription": "L2 cache misses from L1 data cache misses.",
71 "BriefDescription": "L2 cache hits from L1 instruction cache misses.",
77 "BriefDescription": "L2 cache hits from L1 data cache misses.",
120 "BriefDescription": "L1 data cache fills from DRAM or MMIO in any NUMA node.",
126 "BriefDescription": "L1 data cache fills from a different NUMA node.",
132 "BriefDescription": "L1 data cache fills from within the same CCX.",
138 "BriefDescription": "L1 data cache fills from another CCX cache in any NUMA node.",
[all …]
|
| /Linux-v6.6/security/selinux/ss/ |
| D | mls_types.h | 30 static inline int mls_level_eq(const struct mls_level *l1, const struct mls_level *l2) in mls_level_eq() argument
32 return ((l1->sens == l2->sens) && in mls_level_eq()
33 ebitmap_cmp(&l1->cat, &l2->cat)); in mls_level_eq()
36 static inline int mls_level_dom(const struct mls_level *l1, const struct mls_level *l2) in mls_level_dom() argument
38 return ((l1->sens >= l2->sens) && in mls_level_dom()
39 ebitmap_contains(&l1->cat, &l2->cat, 0)); in mls_level_dom()
42 #define mls_level_incomp(l1, l2) \ argument
43 (!mls_level_dom((l1), (l2)) && !mls_level_dom((l2), (l1)))
45 #define mls_level_between(l1, l2, l3) \ argument
46 (mls_level_dom((l1), (l2)) && mls_level_dom((l3), (l1)))
|
| /Linux-v6.6/arch/sparc/kernel/ |
| D | rtrap_64.S | 62 andn %l1, %o0, %l1
85 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
87 and %l1, %l4, %l4
88 andn %l1, %l4, %l1
96 rtrap_nmi: ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
98 and %l1, %l4, %l4
99 andn %l1, %l4, %l1
115 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
118 and %l1, %l4, %l4
119 andn %l1, %l4, %l1
[all …]
|
| D | head_64.S | 169 mov (1b - prom_peer_name), %l1
170 sub %l0, %l1, %l1
174 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "peer"
184 mov (1b - prom_root_node), %l1
185 sub %l0, %l1, %l1
186 stw %l4, [%l1]
188 mov (1b - prom_getprop_name), %l1
191 sub %l0, %l1, %l1
198 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
212 mov (1b - prom_finddev_name), %l1
[all …]
|
| /Linux-v6.6/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/ |
| D | cache.json | 7 …"PublicDescription": "This event counts any refill of the instruction L1 TLB from the L2 TLB. This…
11 …ess which causes data to be read from outside the L1, including accesses which do not allocate int…
15 …ny load or store operation or page table walk access which looks up in the L1 data cache. In parti…
19 …"PublicDescription": "This event counts any refill of the data L1 TLB from the L2 TLB. This includ…
23 …p cache access. This event counts any instruction fetch which accesses the L1 instruction cache or…
27 …"PublicDescription": "This event counts any write-back of data from the L1 data cache to L2 or L3.…
31 …n": "This event counts any transaction from L1 which looks up in the L2 cache, and any write-back …
35 …": "L2 data cache refill. This event counts any cacheable transaction from L1 which causes data to…
39 …ch do not write data outside of the core and snoops which return data from the L1 are not counted",
43 …t cause a linefill, including write-backs from L1 to L2 and full-line writes which do not allocate…
[all …]
|
| /Linux-v6.6/Documentation/virt/kvm/x86/ |
| D | running-nested-guests.rst | 19 | L1 (Guest Hypervisor) |
33 - L1 – level-1 guest; a VM running on L0; also called the "guest
36 - L2 – level-2 guest; a VM running on L1, this is the "nested guest"
45 metal, running the LPAR hypervisor), L1 (host hypervisor), L2
49 L1, and L2) for all architectures; and will largely focus on
148 able to start an L1 guest with::
175 2. The guest hypervisor (L1) must be provided with the ``sie`` CPU
179 3. Now the KVM module can be loaded in the L1 (guest hypervisor)::
187 Migrating an L1 guest, with a *live* nested guest in it, to another
191 On AMD systems, once an L1 guest has started an L2 guest, the L1 guest
[all …]
|
| /Linux-v6.6/tools/perf/pmu-events/arch/x86/amdzen3/ |
| D | recommended.json | 12 "BriefDescription": "All L1 Data Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
124 "BriefDescription": "L1 Data Cache Fills: From Memory",
130 "BriefDescription": "L1 Data Cache Fills: From Remote Node",
136 "BriefDescription": "L1 Data Cache Fills: From within same CCX",
[all …]
|
| D | branch.json | 5 "BriefDescription": "L1 Branch Prediction Overrides Existing Prediction (speculative)."
27 "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB.",
33 …"BriefDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB…
39 …"BriefDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB…
45 …"BriefDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instrcution TLB…
|
| /Linux-v6.6/tools/testing/selftests/powerpc/pmu/event_code_tests/ |
| D | group_constraint_cache_test.c | 13 /* All L1 D cache load references counted at finish, gated by reject */
15 /* Load Missed L1 */
17 /* Load Missed L1 */
23 * Monitor Mode Control Register 1 (MMCR1: 16-17) for l1 cache.
34 /* Init the events for the group contraint check for l1 cache select bits */ in group_constraint_cache()
40 /* Expected to fail as sibling event doesn't request same l1 cache select bits as leader */ in group_constraint_cache()
45 /* Init the event for the group contraint l1 cache select test */ in group_constraint_cache()
48 /* Expected to succeed as sibling event request same l1 cache select bits as leader */ in group_constraint_cache()
|
| /Linux-v6.6/tools/perf/pmu-events/arch/x86/icelakex/ |
| D | memory.json | 115 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the…
124 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the…
133 …on": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.",
142 …n": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches an…
151 …xclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.",
160 …clusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches an…
169 …tion": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that wer…
178 …tion": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that wer…
187 … "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.",
196 …are prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches an…
[all …]
|
| /Linux-v6.6/arch/sparc/lib/ |
| D | xor.S | 370 ldda [%i1 + 0x30] %asi, %l0 /* %l0/%l1 = src + 0x30 */
390 xor %l3, %l1, %l3
418 ldda [%l7 + 0x10] %asi, %l0 /* %l0/%l1 = src2 + 0x10 */
431 xor %l1, %i5, %l1
433 xor %o3, %l1, %o3
437 ldda [%l7 + 0x30] %asi, %l0 /* %l0/%l1 = src2 + 0x30 */
449 xor %l1, %i5, %l1
451 xor %o3, %l1, %o3
482 ldda [%i0 + 0x00] %asi, %l0 /* %l0/%l1 = dest + 0x00 */
490 xor %l1, %g3, %l1
[all …]
|
| /Linux-v6.6/Documentation/devicetree/bindings/regulator/ |
| D | qcom,smd-rpm-regulator.yaml | 27 For pm2250, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
30 For pm6125 s1, s2, s3, s4, s5, s6, s7, s8, l1, l2, l3, l5, l6, l7, l8, l9,
33 For pm660, s1, s2, s3, s4, s5, s6, l1, l2, l3, l5, l6, l7, l8, l9, l10, l22,
36 For pm660l s1, s2, s3, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, bob
38 For pm8226, s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10,
44 For pm8909, s1, s2, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13,
47 For pm8916, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
50 For pm8941, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
54 For pm8950 and pm8953, s1, s2, s3, s4, s5, s6, s7, l1, l2, l3, l4, l5, l6,
58 For pm8994, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3,
[all …]
|
| /Linux-v6.6/tools/perf/pmu-events/arch/arm64/ampere/ampereone/ |
| D | core-imp-def.json | 267 "PublicDescription": "Dispatch stall due to L1 instruction cache miss",
270 "BriefDescription": "Dispatch stall due to L1 instruction cache miss"
273 "PublicDescription": "Dispatch stall due to L1 instruction TLB miss",
276 "BriefDescription": "Dispatch stall due to L1 instruction TLB miss"
279 "PublicDescription": "Dispatch stall due to L1 data cache miss",
282 "BriefDescription": "Dispatch stall due to L1 data cache miss"
285 "PublicDescription": "Dispatch stall due to L1 data TLB miss",
288 "BriefDescription": "Dispatch stall due to L1 data TLB miss"
459 "PublicDescription": "L1 prefetcher, load prefetch requests generated",
462 "BriefDescription": "L1 prefetcher, load prefetch requests generated"
[all …]
|
| /Linux-v6.6/tools/perf/pmu-events/arch/x86/amdzen1/ |
| D | recommended.json | 12 "BriefDescription": "All L1 Data Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
110 "BriefDescription": "L1 Instruction Cache (32B) Fetch Miss Ratio",
117 "BriefDescription": "L1 ITLB Misses",
130 "BriefDescription": "L1 DTLB Misses",
|
| /Linux-v6.6/tools/perf/pmu-events/arch/x86/amdzen2/ |
| D | recommended.json | 12 "BriefDescription": "All L1 Data Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
110 "BriefDescription": "L1 Instruction Cache (32B) Fetch Miss Ratio",
117 "BriefDescription": "L1 ITLB Misses",
130 "BriefDescription": "L1 DTLB Misses",
|
| /Linux-v6.6/drivers/gpu/drm/stm/ |
| D | ltdc.c | 86 #define LTDC_L1C0R (ldev->caps.layer_regs[0]) /* L1 configuration 0 */
87 #define LTDC_L1C1R (ldev->caps.layer_regs[1]) /* L1 configuration 1 */
88 #define LTDC_L1RCR (ldev->caps.layer_regs[2]) /* L1 reload control */
89 #define LTDC_L1CR (ldev->caps.layer_regs[3]) /* L1 control register */
90 #define LTDC_L1WHPCR (ldev->caps.layer_regs[4]) /* L1 window horizontal position configuration */
91 #define LTDC_L1WVPCR (ldev->caps.layer_regs[5]) /* L1 window vertical position configuration */
92 #define LTDC_L1CKCR (ldev->caps.layer_regs[6]) /* L1 color keying configuration */
93 #define LTDC_L1PFCR (ldev->caps.layer_regs[7]) /* L1 pixel format configuration */
94 #define LTDC_L1CACR (ldev->caps.layer_regs[8]) /* L1 constant alpha configuration */
95 #define LTDC_L1DCCR (ldev->caps.layer_regs[9]) /* L1 default color configuration */
[all …]
|
| /Linux-v6.6/fs/ntfs3/ |
| D | upcase.c | 36 int ntfs_cmp_names(const __le16 *s1, size_t l1, const __le16 *s2, size_t l2, in ntfs_cmp_names() argument
41 size_t len = min(l1, l2); in ntfs_cmp_names()
55 return l1 - l2; in ntfs_cmp_names()
65 diff2 = l1 - l2; in ntfs_cmp_names()
74 size_t l1 = uni1->len; in ntfs_cmp_names_cpu() local
76 size_t len = min(l1, l2); in ntfs_cmp_names_cpu()
92 return l1 - l2; in ntfs_cmp_names_cpu()
102 diff2 = l1 - l2; in ntfs_cmp_names_cpu()
|
| /Linux-v6.6/drivers/pci/pcie/ |
| D | aspm.c | 3 * Enable PCIe link L0s/L1 state and Clock Power Management
32 #define ASPM_STATE_L1 (4) /* L1 state */
33 #define ASPM_STATE_L1_1 (8) /* ASPM L1.1 state */
34 #define ASPM_STATE_L1_2 (0x10) /* ASPM L1.2 state */
35 #define ASPM_STATE_L1_1_PCIPM (0x20) /* PCI PM L1.1 state */
36 #define ASPM_STATE_L1_2_PCIPM (0x40) /* PCI PM L1.2 state */
94 * The L1 PM substate capability is only implemented in function 0 in a
114 /* Enable ASPM L0s/L1 */ in policy_to_aspm_state()
285 /* Convert L1 latency encoding to ns */
295 /* Convert L1 acceptable latency encoding to ns */
[all …]
|
| /Linux-v6.6/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| D | other.json | 17 …"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that ha…
26 …"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that we…
35 …"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that we…
44 …"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that we…
161 …"BriefDescription": "Counts data load hardware prefetch requests to the L1 data cache that have an…
188 …are prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches an…
206 …read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any…
215 …read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were sup…
224 …read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were sup…
233 …read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were sup…
[all …]
|
| /Linux-v6.6/arch/powerpc/include/asm/ |
| D | security_features.h | 50 // The L1-D cache can be flushed with ori r30,r30,0
53 // The L1-D cache can be flushed with mtspr 882,r0 (aka SPRN_TRIG2)
62 // Entries in L1-D are private to a SMT thread
76 // The L1-D cache should be flushed on MSR[HV] 1->0 transition (hypervisor to guest)
79 // The L1-D cache should be flushed on MSR[PR] 0->1 transition (kernel to userspace)
94 // The L1-D cache should be flushed when entering the kernel
97 // The L1-D cache should be flushed after user accesses from the kernel
|
| /Linux-v6.6/tools/testing/selftests/kvm/x86_64/ |
| D | vmx_nested_tsc_scaling_test.c | 8 * both L1 and L2 are scaled using different ratios. For this test we scale
9 * L1 down and scale L2 up.
18 /* L2 is scaled up (from L1's perspective) by this factor */
78 /* exit to L1 */ in l2_guest_code()
87 /* check that L1's frequency looks alright before launching L2 */ in l1_guest_code()
113 /* check that L1's frequency still looks good */ in l1_guest_code()
154 * We set L1's scale factor to be a random number from 2 to 10. in main()
161 printf("L1's scale down factor is: %"PRIu64"\n", l1_scale_factor); in main()
178 /* scale down L1's TSC frequency */ in main()
197 printf("L1's TSC frequency is around: %"PRIu64 in main()
|
| /Linux-v6.6/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/ |
| D | cache.json | 108 …scription": "L1 data cache refill due to prefetch. This event counts any linefills from the prefet…
111 …scription": "L1 data cache refill due to prefetch. This event counts any linefills from the prefet…
120 …"PublicDescription": "L1 data cache entering write streaming mode. This event counts for each entr…
123 …"BriefDescription": "L1 data cache entering write streaming mode. This event counts for each entry…
126 …"L1 data cache write streaming mode. This event counts for each cycle where the core is in write s…
129 …"L1 data cache write streaming mode. This event counts for each cycle where the core is in write s…
|
