Lines Matching full:l1
23 "BriefDescription": "L2 cache accesses from L1 instruction cache misses (including prefetch).",
29 "BriefDescription": "L2 cache accesses from L1 data cache misses (including prefetch).",
47 "BriefDescription": "L2 cache misses from L1 instruction cache misses.",
53 "BriefDescription": "L2 cache misses from L1 data cache misses.",
71 "BriefDescription": "L2 cache hits from L1 instruction cache misses.",
77 "BriefDescription": "L2 cache hits from L1 data cache misses.",
120 "BriefDescription": "L1 data cache fills from DRAM or MMIO in any NUMA node.",
126 "BriefDescription": "L1 data cache fills from a different NUMA node.",
132 "BriefDescription": "L1 data cache fills from within the same CCX.",
138 "BriefDescription": "L1 data cache fills from another CCX cache in any NUMA node.",
144 "BriefDescription": "All L1 data cache fills.",
150 "BriefDescription": "L1 demand data cache fills from local L2 cache.",
156 "BriefDescription": "L1 demand data cache fills from within the same CCX.",
162 "BriefDescription": "L1 demand data cache fills from another CCX cache in the same NUMA node.",
168 "BriefDescription": "L1 demand data cache fills from DRAM or MMIO in the same NUMA node.",
174 … "BriefDescription": "L1 demand data cache fills from another CCX cache in a different NUMA node.",
180 "BriefDescription": "L1 demand data cache fills from DRAM or MMIO in a different NUMA node.",
186 "BriefDescription": "L1 instruction TLB misses.",
198 "BriefDescription": "L1 data TLB misses.",