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/Linux-v5.10/Documentation/devicetree/bindings/net/
Dxilinx_gmii2rgmii.txt2 --------------------------------------------------------
4 The Gigabit Media Independent Interface (GMII) to Reduced Gigabit Media
5 Independent Interface (RGMII) core provides the RGMII between RGMII-compliant
8 The Management Data Input/Output (MDIO) interface is used to configure the
18 - compatible : Should be "xlnx,gmii-to-rgmii-1.0"
19 - reg : The ID number for the phy, usually a small integer
20 - phy-handle : Should point to the external phy device.
25 #address-cells = <1>;
26 #size-cells = <0>;
27 phy: ethernet-phy@0 {
[all …]
Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-controller.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
22 LANs. It interfaces directly to twisted pair media via an external
23 transformer. This device interfaces directly to the MAC layer through the
25 Media Independent Interface (GMII) or Reduced GMII (RGMII).
[all …]
Dcpsw.txt2 ------------------------------------------------------
5 - compatible : Should be one of the below:-
7 "ti,am335x-cpsw" for AM335x controllers
8 "ti,am4372-cpsw" for AM437x controllers
9 "ti,dra7-cpsw" for DRA7x controllers
10 - reg : physical base address and size of the cpsw
12 - interrupts : property with a value describing the interrupt
14 - cpdma_channels : Specifies number of channels in CPDMA
15 - ale_entries : Specifies No of entries ALE can hold
16 - bd_ram_size : Specifies internal descriptor RAM size
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Dti,cpsw-switch.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
14 The 3-port switch gigabit ethernet subsystem provides ethernet packet
16 gigabit media independent interface (GMII),reduced gigabit media
17 independent interface (RGMII), reduced media independent interface (RMII),
24 - const: ti,cpsw-switch
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Dsnps,dwc-qos-ethernet.txt3 This binding is deprecated, but it continues to be supported, but new
4 features should be preferably added to the stmmac binding document.
13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
19 This combination is deprecated. It should be treated as equivalent to
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
[all …]
Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
16 local-mac-address:
18 Specifies the MAC address that was assigned to the network device.
19 $ref: /schemas/types.yaml#definitions/uint8-array
21 - minItems: 6
24 mac-address:
[all …]
Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-phy.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
21 This device interfaces to the MAC layer through Reduced GMII (RGMII) and
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Dibm,emac.txt4 the Axon bridge. To operate this needs to interact with a this
5 special McMAL DMA controller, and sometimes an RGMII or ZMII
6 interface. In addition to the nodes and properties described
8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
[all …]
Dti,k3-am654-cpsw-nuss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
16 CPSW2G NUSS features - the Reduced Gigabit Media Independent Interface (RGMII),
21 One external Ethernet port (port 1) with selectable RGMII/RMII interfaces and
25 Peripheral Root Complex (UDMA-P) controller.
39 ingress, Auto VLAN removal on egress and auto pad to minimum frame size.
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/phy/
Dti,phy-gmii-sel.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
15 two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
20 +--------------+
21 +-------------------------------+ |SCM |
22 | CPSW | | +---------+ |
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/Linux-v5.10/arch/mips/include/asm/octeon/
Dcvmx-helper-rgmii.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 * Functions for RGMII/GMII/MII initialization, configuration,
39 * Probe RGMII ports and determine the number present
41 * @interface: Interface to probe
43 * Returns Number of RGMII/GMII/MII ports (0-4).
49 * Put an RGMII interface in loopback mode. Internal packets sent
53 * @port: IPD port number to loop.
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/Linux-v5.10/arch/mips/cavium-octeon/executive/
Dcvmx-helper-rgmii.c7 * Copyright (C) 2003-2018 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 * Functions for RGMII/GMII/MII initialization, configuration,
34 #include <asm/octeon/cvmx-config.h>
36 #include <asm/octeon/cvmx-pko.h>
37 #include <asm/octeon/cvmx-helper.h>
38 #include <asm/octeon/cvmx-helper-board.h>
40 #include <asm/octeon/cvmx-npi-defs.h>
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Dcvmx-helper.c7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
36 #include <asm/octeon/cvmx-config.h>
38 #include <asm/octeon/cvmx-fpa.h>
39 #include <asm/octeon/cvmx-pip.h>
40 #include <asm/octeon/cvmx-pko.h>
41 #include <asm/octeon/cvmx-ipd.h>
42 #include <asm/octeon/cvmx-spi.h>
[all …]
Dcvmx-interrupt-rsl.c7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 * Utility functions to decode Octeon's RSL_INT_BLOCKS
35 #include <asm/octeon/cvmx-asxx-defs.h>
36 #include <asm/octeon/cvmx-gmxx-defs.h>
48 * @block: Interface to enable 0-1
74 * @interface: Interface to enable
107 * errors through port 0. RGMII needs in __cvmx_interrupt_gmxx_enable()
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
Ducc.txt4 - device_type : should be "network", "hldc", "uart", "transparent"
6 - compatible : could be "ucc_geth" or "fsl_atm" and so on.
7 - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
8 - reg : Offset and length of the register set for the device
9 - interrupts : <a b> where a is the interrupt number and b is a
14 - pio-handle : The phandle for the Parallel I/O port configuration.
15 - port-number : for UART drivers, the port number to use, between 0 and 3.
16 This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0.
17 The port number is added to the minor number of the device. Unlike the
18 CPM UART driver, the port-number is required for the QE UART driver.
[all …]
/Linux-v5.10/Documentation/ABI/testing/
Dsysfs-class-net-phydev6 Symbolic link to the network device this PHY device is
7 attached to.
16 a boolean. This information is provided to help troubleshooting
24 This attribute contains the 32-bit PHY Identifier as reported
26 This ID is used to match the device with the appropriate
36 This interface mode is used to configure the Ethernet MAC with the
37 appropriate mode for its data lines to the PHY hardware.
41 <empty> (not available), mii, gmii, sgmii, tbi, rev-mii,
42 rmii, rgmii, rgmii-id, rgmii-rxid, rgmii-txid, rtbi, smii
43 xgmii, moca, qsgmii, trgmii, 1000base-x, 2500base-x, rxaui,
[all …]
/Linux-v5.10/drivers/clk/sunxi/
Dclk-a20-gmac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2013 Chen-Yu Tsai
7 * Chen-Yu Tsai <wens@csie.org>
10 #include <linux/clk-provider.h>
19 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
23 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
24 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
25 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
32 * To keep it simple, let the GMAC use either the MII TX clock for MII mode,
33 * and its internal TX clock for GMII and RGMII modes. The GMAC driver should
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Dgemini-sq201.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
9 #include <dt-bindings/input/input.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
24 stdout-path = &uart0;
28 compatible = "gpio-keys";
30 button-setup {
31 debounce-interval = <100>;
32 wakeup-source;
[all …]
Dgemini-nas4220b.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for the Gemini-based Raidsonic NAS IB-4220-B
6 /dts-v1/;
9 #include <dt-bindings/input/input.h>
12 model = "Raidsonic NAS IB-4220-B";
13 compatible = "raidsonic,ib-4220-b", "cortina,gemini";
14 #address-cells = <1>;
15 #size-cells = <1>;
24 stdout-path = &uart0;
28 compatible = "gpio-keys";
[all …]
/Linux-v5.10/drivers/net/ethernet/stmicro/stmmac/
Ddwmac1000.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
86 #define GMAC_RGSMIIIS 0x000000d8 /* RGMII/SMII status */
88 /* SGMII/RGMII status register */
105 #define GMAC_CONTROL_TC 0x01000000 /* Transmit Conf. in RGMII/SGMII */
119 #define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
144 /* GMII ADDR defines */
175 /* MAC GMII or MII Transmit Protocol Engine Status */
177 #define GMAC_DEBUG_RXFSTS_MASK GENMASK(9, 8) /* MTL Rx FIFO Fill-level */
[all …]
/Linux-v5.10/drivers/net/ethernet/ibm/emac/
Drgmii.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/net/ethernet/ibm/emac/rgmii.c
5 * Driver for PowerPC 4xx on-chip ethernet controller, RGMII bridge support.
28 // XXX FIXME: Axon seems to support a subset of the RGMII, we
29 // thus need to take that into account and possibly change some
30 // of the bit settings below that don't seem to quite match the
47 /* RGMII bridge supports only GMII/TBI and RGMII/RTBI PHYs */
81 struct rgmii_regs __iomem *p = dev->base; in rgmii_attach()
85 /* Check if we need to attach to a RGMII */ in rgmii_attach()
88 ofdev->dev.of_node); in rgmii_attach()
[all …]
/Linux-v5.10/include/linux/ssb/
Dssb_driver_gige.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define SSB_GIGE_SHIM_FLUSHSTAT 0x0C00 /* PCI to OCP: Flush status control (32bit) */
18 #define SSB_GIGE_SHIM_FLUSHRDA 0x0C04 /* PCI to OCP: Flush read address (32bit) */
19 #define SSB_GIGE_SHIM_FLUSHTO 0x0C08 /* PCI to OCP: Flush timeout counter (32bit) */
20 #define SSB_GIGE_SHIM_BARRIER 0x0C0C /* PCI to OCP: Barrier register (32bit) */
21 #define SSB_GIGE_SHIM_MAOCPSI 0x0C10 /* PCI to OCP: MaocpSI Control (32bit) */
22 #define SSB_GIGE_SHIM_SIOCPMA 0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */
25 #define SSB_GIGE_TMSHIGH_RGMII 0x00010000 /* Have an RGMII PHY-bus */
43 /* True, if the device has an RGMII bus.
44 * False, if the device has a GMII bus. */
[all …]
/Linux-v5.10/drivers/staging/octeon/
Dethernet-rgmii.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2003-2007 Cavium Networks
15 #include "octeon-ethernet.h"
16 #include "ethernet-defines.h"
17 #include "ethernet-util.h"
18 #include "ethernet-mdio.h"
27 int interface = INTERFACE(priv->port); in cvm_oct_set_hw_preamble()
28 int index = INDEX(priv->port); in cvm_oct_set_hw_preamble()
40 ipd_sub_port_fcs.s.port_bit |= 1ull << priv->port; in cvm_oct_set_hw_preamble()
43 0xffffffffull ^ (1ull << priv->port); in cvm_oct_set_hw_preamble()
[all …]
/Linux-v5.10/Documentation/networking/dsa/
Dbcm_sf2.rst8 - xDSL gateways such as BCM63138
9 - streaming/multimedia Set Top Box such as BCM7445
10 - Cable Modem/residential gateways such as BCM7145/BCM3390
12 The switch is typically deployed in a configuration involving between 5 to 13
13 ports, offering a range of built-in and customizable interfaces:
15 - single integrated Gigabit PHY
16 - quad integrated Gigabit PHY
17 - quad external Gigabit PHY w/ MDIO multiplexer
18 - integrated MoCA PHY
19 - several external MII/RevMII/GMII/RGMII interfaces
[all …]
/Linux-v5.10/arch/powerpc/platforms/83xx/
Dmpc836x_mds.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Yin Olivia <Hong-hua.Yin@freescale.com>
104 /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */ in mpc836x_mds_setup_arch()
142 np = of_find_compatible_node(NULL, NULL, "fsl,mpc8360mds-bcsr"); in mpc836x_usb_cfg()
144 return -ENODEV; in mpc836x_usb_cfg()
149 return -ENOMEM; in mpc836x_usb_cfg()
151 np = of_find_compatible_node(NULL, NULL, "fsl,mpc8323-qe-usb"); in mpc836x_usb_cfg()
153 ret = -ENODEV; in mpc836x_usb_cfg()
162 * Default is GMII (2), but we should set it to RGMII (0) if we use in mpc836x_usb_cfg()
163 * USB (Eth PHY is in RGMII mode anyway). in mpc836x_usb_cfg()
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