Lines Matching +full:gmii +full:- +full:to +full:- +full:rgmii

1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define SSB_GIGE_SHIM_FLUSHSTAT		0x0C00 /* PCI to OCP: Flush status control (32bit) */
18 #define SSB_GIGE_SHIM_FLUSHRDA		0x0C04 /* PCI to OCP: Flush read address (32bit) */
19 #define SSB_GIGE_SHIM_FLUSHTO		0x0C08 /* PCI to OCP: Flush timeout counter (32bit) */
20 #define SSB_GIGE_SHIM_BARRIER		0x0C0C /* PCI to OCP: Barrier register (32bit) */
21 #define SSB_GIGE_SHIM_MAOCPSI		0x0C10 /* PCI to OCP: MaocpSI Control (32bit) */
22 #define SSB_GIGE_SHIM_SIOCPMA		0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */
25 #define SSB_GIGE_TMSHIGH_RGMII		0x00010000 /* Have an RGMII PHY-bus */
43 	/* True, if the device has an RGMII bus.
44 	 * False, if the device has a GMII bus. */
57 /* Convert a pci_dev pointer to a ssb_gige pointer. */
62 	return container_of(pdev->bus->ops, struct ssb_gige, pci_ops);  in pdev_to_ssb_gige()
65 /* Returns whether the PHY is connected by an RGMII bus. */
69 	return (dev ? dev->has_rgmii : 0);  in ssb_gige_is_rgmii()
77 		return !!(dev->dev->bus->sprom.boardflags_lo &  in ssb_gige_have_roboswitch()
87 		return ((dev->dev->bus->chip_id == 0x4785) &&  in ssb_gige_one_dma_at_once()
88 			(dev->dev->bus->chip_rev < 2));  in ssb_gige_one_dma_at_once()
97 		return (dev->dev->bus->chip_id == 0x4785);  in ssb_gige_must_flush_posted_writes()
106 		return -ENODEV;  in ssb_gige_get_macaddr()
108 	memcpy(macaddr, dev->dev->bus->sprom.et0mac, 6);  in ssb_gige_get_macaddr()
117 		return -ENODEV;  in ssb_gige_get_phyaddr()
119 	return dev->dev->bus->sprom.et0phyaddr;  in ssb_gige_get_phyaddr()
145 	return -ENOSYS;  in ssb_gige_pcibios_plat_dev_init()
150 	return -ENOSYS;  in ssb_gige_map_irq()
186 	return -ENODEV;  in ssb_gige_get_macaddr()
190 	return -ENODEV;  in ssb_gige_get_phyaddr()