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/Linux-v5.10/arch/x86/include/asm/
Dsysfb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
7 * Copyright (c) 2012-2013 David Herrmann <dh.herrmann@gmail.com>
15 M_I17, /* 17-Inch iMac */
16 M_I20, /* 20-Inch iMac */
17 M_I20_SR, /* 20-Inch iMac (Santa Rosa) */
18 M_I24, /* 24-Inch iMac */
19 M_I24_8_1, /* 24-Inch iMac, 8,1th gen */
20 M_I24_10_1, /* 24-Inch iMac, 10,1th gen */
21 M_I27_11_1, /* 27-Inch iMac, 11,1th gen */
23 M_MINI_3_1, /* Mac Mini, 3,1th gen */
[all …]
/Linux-v5.10/drivers/net/dsa/sja1105/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
10 family. These are 5-port devices and are managed over an SPI
13 - SJA1105E (Gen. 1, No TT-Ethernet)
14 - SJA1105T (Gen. 1, TT-Ethernet)
15 - SJA1105P (Gen. 2, No SGMII, No TT-Ethernet)
16 - SJA1105Q (Gen. 2, No SGMII, TT-Ethernet)
17 - SJA1105R (Gen. 2, SGMII, No TT-Ethernet)
18 - SJA1105S (Gen. 2, SGMII, TT-Ethernet)
29 bool "Support for the Time-Aware Scheduler on NXP SJA1105"
34 This enables support for the TTEthernet-based egress scheduling
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/Linux-v5.10/sound/pci/hda/
Dpatch_analog.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (c) 2005-2007 Takashi Iwai <tiwai@suse.de>
23 struct hda_gen_spec gen; member
44 ((spec)->beep_amp = HDA_COMPOSE_AMP_VAL(nid, 1, idx, dir)) /* mono */
52 struct ad198x_spec *spec = codec->spec; in create_beep_ctls()
55 if (!spec->beep_amp) in create_beep_ctls()
58 for (knew = ad_beep_mixer ; knew->name; knew++) { in create_beep_ctls()
63 return -ENOMEM; in create_beep_ctls()
64 kctl->private_value = spec->beep_amp; in create_beep_ctls()
81 !codec->inv_eapd ? 0x00 : 0x02); in ad198x_power_eapd_write()
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Dpatch_via.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * (C) 2006-2009 VIA Technology, Inc.
8 * (C) 2006-2008 Takashi Iwai <tiwai@suse.de>
13 /* 2006-03-03 Lydia Wang Create the basic patch to support VT1708 codec */
14 /* 2006-03-14 Lydia Wang Modify hard code for some pin widget nid */
15 /* 2006-08-02 Lydia Wang Add support to VT1709 codec */
16 /* 2006-09-08 Lydia Wang Fix internal loopback recording source select bug */
17 /* 2007-09-12 Lydia Wang Add EAPD enable during driver initialization */
18 /* 2007-09-17 Lydia Wang Add VT1708B codec support */
19 /* 2007-11-14 Lydia Wang Add VT1708A codec HP and CD pin connect config */
[all …]
Dpatch_cirrus.c1 // SPDX-License-Identifier: GPL-2.0-or-later
23 struct hda_gen_spec gen; member
65 /* Vendor-specific processing widget */
78 * 1 = digital immediate, analog zero-cross
79 * 2 = digtail & analog soft-ramp
80 * 3 = digital soft-ramp, analog zero-cross
84 #define CS_COEF_ADC_LI_SZC_MODE (3 << 0) /* SZC setup for line-in */
85 /* PGA mode: 0 = differential, 1 = signle-ended */
87 #define CS_COEF_ADC_LI_PGA_MODE (1 << 6) /* PGA setup for line-in */
91 * 1 = zero-cross
[all …]
Dpatch_conexant.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Tobin Davis <tdavis@dsl-only.net>
25 struct hda_gen_spec gen; member
63 spec->gen.beep_nid = nid; in set_beep_amp()
65 knew = snd_hda_gen_add_kctl(&spec->gen, NULL, in set_beep_amp()
68 return -ENOMEM; in set_beep_amp()
69 knew->private_value = beep_amp; in set_beep_amp()
76 struct conexant_spec *spec = codec->spec; in cx_auto_parse_beep()
95 struct conexant_spec *spec = codec->spec; in cx_auto_parse_eapd()
103 spec->eapds[spec->num_eapds++] = nid; in cx_auto_parse_eapd()
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/Linux-v5.10/drivers/gpu/drm/rcar-du/
Drcar_du_drv.c1 // SPDX-License-Identifier: GPL-2.0+
3 * rcar_du_drv.c -- R-Car Display Unit DRM driver
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
32 /* -----------------------------------------------------------------------------
37 .gen = 2,
59 .gen = 2,
80 .gen = 2,
100 .port = 2,
106 .gen = 3,
111 .channels_mask = BIT(2) | BIT(1) | BIT(0),
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Drcar_du_group.c1 // SPDX-License-Identifier: GPL-2.0+
3 * rcar_du_group.c -- R-Car Display Unit Channels Pair
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
11 * The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending
12 * unit, timings generator, ...) and device-global resources (start/stop
19 * modeled as a single device with three CRTCs, two sets of "semi-global"
20 * resources, and a few device-global resources.
23 * counterpart in the DU documentation, that models those semi-global resources.
35 return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg); in rcar_du_group_read()
40 rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data); in rcar_du_group_write()
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/Linux-v5.10/drivers/gpu/drm/i915/gt/
Dselftest_engine_cs.c2 * SPDX-License-Identifier: GPL-2.0
21 return *a - *b; in cmp_u32()
29 atomic_inc(&gt->rps.num_waiters); in perf_begin()
30 schedule_work(&gt->rps.work); in perf_begin()
31 flush_work(&gt->rps.work); in perf_begin()
36 atomic_dec(&gt->rps.num_waiters); in perf_end()
39 return igt_flush_test(gt->i915); in perf_end()
52 if (INTEL_GEN(rq->engine->i915) >= 8) in write_timestamp()
55 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base)); in write_timestamp()
56 *cs++ = i915_request_timeline(rq)->hwsp_offset + slot * sizeof(u32); in write_timestamp()
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/Linux-v5.10/drivers/rapidio/switches/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 tristate "IDT CPS-xx SRIO switches support"
13 Includes support for IDT CPS-16/12/10/8 serial RapidIO switches.
22 tristate "IDT CPS Gen.2 SRIO switch support"
25 Includes support for ITD CPS Gen.2 serial RapidIO switches.
28 tristate "IDT RXS Gen.3 SRIO switch support"
31 Includes support for ITD RXS Gen.3 serial RapidIO switches.
/Linux-v5.10/arch/arm64/boot/dts/mediatek/
Dmt8173-elm-hana.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "mt8173-elm.dtsi"
9 clock-frequency = <200000>;
16 interrupt-parent = <&pio>;
21 * Lenovo 100e Chromebook 2nd Gen (MTK) and Lenovo 300e Chromebook 2nd
22 * Gen (MTK) are using synaptics touchscreen (hid-over-i2c driver) as a
26 compatible = "hid-over-i2c";
28 hid-descr-addr = <0x0020>;
29 interrupt-parent = <&pio>;
36 * Lenovo 100e Chromebook 2nd Gen (MTK) and Lenovo 300e Chromebook 2nd
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/Linux-v5.10/drivers/net/vmxnet3/
Dvmxnet3_defs.h4 * Copyright (C) 2008-2020, VMware, Inc. All Rights Reserved.
8 * Free Software Foundation; version 2 of the License and no later version.
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23 * Maintained by: pv-drivers@vmware.com
51 VMXNET3_REG_RXPROD2 = 0xA00 /* Rx Producer Index for ring 2 */
57 #define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */
104 * Little Endian layout of bitfields -
106 * Byte 1 : oco gen 13.len.8
107 * Byte 2 : 5.msscof.0 ext1 dtype
110 * Big Endian layout of bitfields -
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/Linux-v5.10/arch/x86/events/intel/
Duncore_snb.c1 // SPDX-License-Identifier: GPL-2.0
93 #define SNB_UNC_GLOBAL_CTL_CORE_ALL ((1 << 4) - 1)
112 #define NHM_UNC_GLOBAL_CTL_EN_PC_ALL ((1ULL << 8) - 1)
121 #define SKL_UNC_GLOBAL_CTL_CORE_ALL ((1 << 5) - 1)
133 DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
134 DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
137 DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
138 DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
143 struct hw_perf_event *hwc = &event->hw; in snb_uncore_msr_enable_event()
145 if (hwc->idx < UNCORE_PMC_IDX_FIXED) in snb_uncore_msr_enable_event()
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/Linux-v5.10/arch/s390/kernel/syscalls/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 gen := arch/$(ARCH)/include/generated macro
4 kapi := $(gen)/asm
5 uapi := $(gen)/uapi/asm
10 gen-y := $(kapi)/syscall_table.h
11 kapi-hdrs-y := $(kapi)/unistd_nr.h
12 uapi-hdrs-y := $(uapi)/unistd_32.h
13 uapi-hdrs-y += $(uapi)/unistd_64.h
15 targets += $(addprefix ../../../,$(gen-y) $(kapi-hdrs-y) $(uapi-hdrs-y))
19 kapi: $(gen-y) $(kapi-hdrs-y)
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/Linux-v5.10/drivers/base/firmware_loader/builtin/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Create $(fwdir) from $(CONFIG_EXTRA_FIRMWARE_DIR) -- if it doesn't have a
6 fwdir := $(addprefix $(srctree)/,$(filter-out /%,$(fwdir)))$(filter /%,$(fwdir))
8 obj-y := $(addsuffix .gen.o, $(subst $(quote),,$(CONFIG_EXTRA_FIRMWARE)))
10 FWNAME = $(patsubst $(obj)/%.gen.S,%,$@)
12 FWSTR = $(subst $(comma),_,$(subst /,_,$(subst .,_,$(subst -,_,$(FWNAME)))))
14 ASM_ALIGN = $(if $(CONFIG_64BIT),3,2)
32 echo " $(ASM_WORD) _fw_end - _fw_$(FWSTR)_bin"
34 $(obj)/%.gen.S: FORCE
38 $(addprefix $(obj)/, $(obj-y)): $(obj)/%.gen.o: $(fwdir)/%
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/Linux-v5.10/drivers/phy/st/
Dphy-miphy28lp.c1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <dt-bindings/phy/phy.h>
30 #define RST_MACRO_SW BIT(2)
34 #define RST_COMP_SW BIT(2)
39 #define HFC_PLL BIT(2)
42 #define TERM_EN_SW BIT(2)
54 #define SSC_EN_SW BIT(2)
60 #define TX_SPDSEL_20DEC 2
62 #define RX_SPDSEL_40DEC (1 << 2)
63 #define RX_SPDSEL_20DEC (2 << 2)
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/Linux-v5.10/drivers/gpu/drm/i915/
Di915_pci.c39 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1) macro
151 /* Keep in gen based order, and chronological order within a gen */
160 GEN(2), \
182 GEN(2), \
224 GEN(3), \
314 GEN(4), \
367 GEN(5), \
397 GEN(6), \
428 .gt = 2,
444 .gt = 2,
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/Linux-v5.10/drivers/net/ethernet/chelsio/cxgb3/
Dsge.c2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
6 * General Public License (GPL) Version 2, available from the file
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
38 #include <linux/dma-mapping.h>
135 * This structure lives at skb->head and must be allocated by callers.
146 * desc = 1 + (flits - 2) / (WR_FLITS - 1).
154 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
157 #elif SGE_NUM_GENBITS == 2
159 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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/Linux-v5.10/tools/testing/selftests/vm/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 uname_M := $(shell uname -m 2>/dev/null || echo not)
4 MACHINE ?= $(shell echo $(uname_M) | sed -e 's/aarch64.*/arm64/')
6 # Without this, failed build products remain, with up-to-date timestamps,
11 # Avoid accidental wrong builds, due to built-in rules working just a little
12 # bit too well--but not quite as well as required for our situation here.
16 # However, the built-in rules, if not suppressed, will pick up CFLAGS and the
17 # initial LDLIBS (but not the target-specific LDLIBS, because those are only
21 MAKEFLAGS += --no-builtin-rules
23 CFLAGS = -Wall -I ../../../../usr/include $(EXTRA_CFLAGS)
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/Linux-v5.10/drivers/clk/tegra/
Dclk-tegra-super-gen4.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
15 #include "clk-id.h"
36 enum tegra_super_gen gen; member
60 .gen = gen4,
86 .gen = gen5,
106 gen_info->sclk_parents, in tegra_sclk_init()
107 gen_info->num_sclk_parents, in tegra_sclk_init()
128 gen_info->sclk_parents, in tegra_sclk_init()
129 gen_info->num_sclk_parents, in tegra_sclk_init()
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/Linux-v5.10/drivers/scsi/
Dgdth.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
9 * Copyright (C) 2002-04 Intel Corporation *
10 * Copyright (C) 2003-06 Adaptec Inc. *
33 * reserve_mode:2 reserve all not init. drives
35 * h- controller no., b- channel no.,
36 * t- target ID, l- LUN
39 * max_ids:x x - target ID count per channel (1..MAXID)
42 * hdr_channel:x x - number of virtual bus for host drives
53 * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
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/Linux-v5.10/tools/testing/selftests/x86/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
8 UNAME_M := $(shell uname -m)
9 CAN_BUILD_I386 := $(shell ./check_cc.sh $(CC) trivial_32bit_program.c -m32)
11 CAN_BUILD_WITH_NOPIE := $(shell ./check_cc.sh $(CC) trivial_program.c -no-pie)
36 CFLAGS := -O2 -g -std=gnu99 -pthread -Wall
40 CFLAGS += -no-pie
43 define gen-target-rule-32
48 define gen-target-rule-64
56 EXTRA_CFLAGS += -DCAN_BUILD_32
57 $(foreach t,$(TARGETS_C_32BIT_ALL),$(eval $(call gen-target-rule-32,$(t))))
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/Linux-v5.10/arch/powerpc/kvm/
Dbookehv_interrupts.S1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
17 #include <asm/asm-compat.h>
18 #include <asm/asm-offsets.h>
22 #include <asm/exception-64e.h>
39 * kernel with the -ffixed-r2 gcc option.
44 #define __HOST_NV_GPR(n) (HOST_NV_GPRS + ((n - 14) * LONGBYTES))
51 #define NEED_EMU 0x00000001 /* emulation -- save nv regs */
58 * saved in vcpu: cr, ctr, r3-r13
74 PPC_STL r14, VCPU_GPR(R14)(r4) /* We need a non-volatile GPR. */
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/Linux-v5.10/drivers/pci/controller/
Dpci-aardvark.c1 // SPDX-License-Identifier: GPL-2.0
28 #include "../pci-bridge-emul.h"
35 #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
44 #define PCIE_CORE_INT_B_ASSERT_ENABLE 2
57 #define PIO_COMPLETION_STATUS_CRS 2
76 #define SPEED_GEN_3 2
78 #define IS_RC_SHIFT 2
83 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
176 #define PIO_RETRY_DELAY 2 /* 2 us*/
207 writel(val, pcie->base + reg); in advk_writel()
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/Linux-v5.10/tools/bpf/bpftool/Documentation/
Dbpftool-gen.rst2 bpftool-gen
4 -------------------------------------------------------------------------------
5 tool for BPF code-generation
6 -------------------------------------------------------------------------------
13 **bpftool** [*OPTIONS*] **gen** *COMMAND*
15 *OPTIONS* := { { **-j** | **--json** } [{ **-p** | **--pretty** }] }
19 GEN COMMANDS
22 | **bpftool** **gen skeleton** *FILE*
23 | **bpftool** **gen help**
27 **bpftool gen skeleton** *FILE*
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