1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <dt-bindings/phy/phy.h>
30 #define RST_MACRO_SW		BIT(2)
34 #define RST_COMP_SW		BIT(2)
39 #define HFC_PLL			BIT(2)
42 #define TERM_EN_SW		BIT(2)
54 #define SSC_EN_SW		BIT(2)
60 #define TX_SPDSEL_20DEC		2
62 #define RX_SPDSEL_40DEC		(1 << 2)
63 #define RX_SPDSEL_20DEC		(2 << 2)
89 #define TX_REG_STEP_P_50MV	2
97 #define TX_SLEW_SW_120_PS	2
117 #define EQ_DC_GAIN		BIT(2)
129 #define CAL_OFFSET_THRESHOLD_64	(0x03 << 2)
146 #define EN_SECOND_HALF		BIT(2)
170  *  0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
172  *  1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
180 #define MIPHY_CTRL_SYNC_D_EN	BIT(2)
191 #define MIPHY_PCIE_BANK_NB	2
237 static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" };
366 	void __iomem *base = miphy_phy->base;  in miphy28lp_set_reset()
377 	/* Bringing the MIPHY-CPU registers out of reset */  in miphy28lp_set_reset()
378 	if (miphy_phy->type == PHY_TYPE_PCIE) {  in miphy28lp_set_reset()
390 	void __iomem *base = miphy_phy->base;  in miphy28lp_pll_calibration()
395 	writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ);  in miphy28lp_pll_calibration()
398 	writeb_relaxed(pll_ratio->calset_1, base + MIPHY_PLL_CALSET_1);  in miphy28lp_pll_calibration()
399 	writeb_relaxed(pll_ratio->calset_2, base + MIPHY_PLL_CALSET_2);  in miphy28lp_pll_calibration()
400 	writeb_relaxed(pll_ratio->calset_3, base + MIPHY_PLL_CALSET_3);  in miphy28lp_pll_calibration()
401 	writeb_relaxed(pll_ratio->calset_4, base + MIPHY_PLL_CALSET_4);  in miphy28lp_pll_calibration()
402 	writeb_relaxed(pll_ratio->cal_ctrl, base + MIPHY_PLL_CALSET_CTRL);  in miphy28lp_pll_calibration()
411 	if (miphy_phy->type != PHY_TYPE_SATA)  in miphy28lp_pll_calibration()
416 	if (miphy_phy->type == PHY_TYPE_USB3) {  in miphy28lp_pll_calibration()
431 	void __iomem *base = miphy_phy->base;  in miphy28lp_sata_config_gen()
435 		struct miphy28lp_pll_gen *gen = &sata_pll_gen[i];  in miphy28lp_sata_config_gen()  local
438 		writeb_relaxed(gen->bank, base + MIPHY_CONF);  in miphy28lp_sata_config_gen()
439 		writeb_relaxed(gen->speed, base + MIPHY_SPEED);  in miphy28lp_sata_config_gen()
440 		writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1);  in miphy28lp_sata_config_gen()
441 		writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2);  in miphy28lp_sata_config_gen()
444 		writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2);  in miphy28lp_sata_config_gen()
445 		writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3);  in miphy28lp_sata_config_gen()
448 		writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL);  in miphy28lp_sata_config_gen()
449 		writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN);  in miphy28lp_sata_config_gen()
450 		writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1);  in miphy28lp_sata_config_gen()
451 		writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2);  in miphy28lp_sata_config_gen()
452 		writeb_relaxed(gen->rx_equ_gain_3, base + MIPHY_RX_EQU_GAIN_3);  in miphy28lp_sata_config_gen()
458 	void __iomem *base = miphy_phy->base;  in miphy28lp_pcie_config_gen()
462 		struct miphy28lp_pll_gen *gen = &pcie_pll_gen[i];  in miphy28lp_pcie_config_gen()  local
465 		writeb_relaxed(gen->bank, base + MIPHY_CONF);  in miphy28lp_pcie_config_gen()
466 		writeb_relaxed(gen->speed, base + MIPHY_SPEED);  in miphy28lp_pcie_config_gen()
467 		writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1);  in miphy28lp_pcie_config_gen()
468 		writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2);  in miphy28lp_pcie_config_gen()
471 		writeb_relaxed(gen->tx_ctrl_1, base + MIPHY_TX_CTRL_1);  in miphy28lp_pcie_config_gen()
472 		writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2);  in miphy28lp_pcie_config_gen()
473 		writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3);  in miphy28lp_pcie_config_gen()
475 		writeb_relaxed(gen->rx_k_gain, base + MIPHY_RX_K_GAIN);  in miphy28lp_pcie_config_gen()
478 		writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL);  in miphy28lp_pcie_config_gen()
479 		writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN);  in miphy28lp_pcie_config_gen()
480 		writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1);  in miphy28lp_pcie_config_gen()
481 		writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2);  in miphy28lp_pcie_config_gen()
492 		val = readb_relaxed(miphy_phy->base + MIPHY_COMP_FSM_6);  in miphy28lp_wait_compensation()
495 			return -EBUSY;  in miphy28lp_wait_compensation()
506 	void __iomem *base = miphy_phy->base;  in miphy28lp_compensation()
513 	writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ);  in miphy28lp_compensation()
516 	if (miphy_phy->type == PHY_TYPE_PCIE)  in miphy28lp_compensation()
523 	/* TX compensation offset to re-center TX impedance */  in miphy28lp_compensation()
526 	if (miphy_phy->type == PHY_TYPE_PCIE)  in miphy28lp_compensation()
534 	void __iomem *base = miphy_phy->base;  in miphy28_usb3_miphy_reset()
562 	void __iomem *base = miphy_phy->base;  in miphy_sata_tune_ssc()
600 	void __iomem *base = miphy_phy->base;  in miphy_pcie_tune_ssc()
641 	writeb_relaxed(0x02, miphy_phy->base + MIPHY_COMP_POSTP);  in miphy_tune_tx_impedance()
646 	void __iomem *base = miphy_phy->base;  in miphy28lp_configure_sata()
672 	if (miphy_phy->px_rx_pol_inv) {  in miphy28lp_configure_sata()
674 		val = readb_relaxed(miphy_phy->base + MIPHY_CONTROL);  in miphy28lp_configure_sata()
676 		writeb_relaxed(val, miphy_phy->base + MIPHY_CONTROL);  in miphy28lp_configure_sata()
679 	if (miphy_phy->ssc)  in miphy28lp_configure_sata()
682 	if (miphy_phy->tx_impedance)  in miphy28lp_configure_sata()
690 	void __iomem *base = miphy_phy->base;  in miphy28lp_configure_pcie()
715 	if (miphy_phy->ssc)  in miphy28lp_configure_pcie()
718 	if (miphy_phy->tx_impedance)  in miphy28lp_configure_pcie()
727 	void __iomem *base = miphy_phy->base;  in miphy28lp_configure_usb3()
758 	/* TX compensation offset to re-center TX impedance */  in miphy28lp_configure_usb3()
816 	if (miphy_phy->type == PHY_TYPE_SATA)  in miphy_is_ready()
820 		val = readb_relaxed(miphy_phy->base + MIPHY_STATUS_1);  in miphy_is_ready()
827 	return -EBUSY;  in miphy_is_ready()
832 	struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;  in miphy_osc_is_ready()
836 	if (!miphy_phy->osc_rdy)  in miphy_osc_is_ready()
839 	if (!miphy_phy->syscfg_reg[SYSCFG_STATUS])  in miphy_osc_is_ready()
840 		return -EINVAL;  in miphy_osc_is_ready()
843 		regmap_read(miphy_dev->regmap,  in miphy_osc_is_ready()
844 				miphy_phy->syscfg_reg[SYSCFG_STATUS], &val);  in miphy_osc_is_ready()
852 	return -EBUSY;  in miphy_osc_is_ready()
860 	index = of_property_match_string(child, "reg-names", rname);  in miphy28lp_get_resource_byname()
862 		return -ENODEV;  in miphy28lp_get_resource_byname()
880 			return -ENOENT;  in miphy28lp_get_one_addr()
891 	struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;  in miphy28lp_setup()
893 	if (!miphy_phy->syscfg_reg[SYSCFG_CTRL])  in miphy28lp_setup()
894 		return -EINVAL;  in miphy28lp_setup()
896 	err = reset_control_assert(miphy_phy->miphy_rst);  in miphy28lp_setup()
898 		dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n");  in miphy28lp_setup()
902 	if (miphy_phy->osc_force_ext)  in miphy28lp_setup()
905 	regmap_update_bits(miphy_dev->regmap,  in miphy28lp_setup()
906 			   miphy_phy->syscfg_reg[SYSCFG_CTRL],  in miphy28lp_setup()
909 	err = reset_control_deassert(miphy_phy->miphy_rst);  in miphy28lp_setup()
911 		dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n");  in miphy28lp_setup()
920 	struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;  in miphy28lp_init_sata()
923 	if ((!miphy_phy->syscfg_reg[SYSCFG_SATA]) ||  in miphy28lp_init_sata()
924 			(!miphy_phy->syscfg_reg[SYSCFG_PCI]) ||  in miphy28lp_init_sata()
925 			(!miphy_phy->base))  in miphy28lp_init_sata()
926 		return -EINVAL;  in miphy28lp_init_sata()
928 	dev_info(miphy_dev->dev, "sata-up mode, addr 0x%p\n", miphy_phy->base);  in miphy28lp_init_sata()
930 	/* Configure the glue-logic */  in miphy28lp_init_sata()
931 	sata_conf |= ((miphy_phy->sata_gen - SATA_GEN1) << SATA_SPDMODE);  in miphy28lp_init_sata()
933 	regmap_update_bits(miphy_dev->regmap,  in miphy28lp_init_sata()
934 			   miphy_phy->syscfg_reg[SYSCFG_SATA],  in miphy28lp_init_sata()
937 	regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_reg[SYSCFG_PCI],  in miphy28lp_init_sata()
944 		dev_err(miphy_dev->dev, "SATA phy setup failed\n");  in miphy28lp_init_sata()
956 	struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;  in miphy28lp_init_pcie()
959 	if ((!miphy_phy->syscfg_reg[SYSCFG_SATA]) ||  in miphy28lp_init_pcie()
960 			(!miphy_phy->syscfg_reg[SYSCFG_PCI])  in miphy28lp_init_pcie()
961 		|| (!miphy_phy->base) || (!miphy_phy->pipebase))  in miphy28lp_init_pcie()
962 		return -EINVAL;  in miphy28lp_init_pcie()
964 	dev_info(miphy_dev->dev, "pcie-up mode, addr 0x%p\n", miphy_phy->base);  in miphy28lp_init_pcie()
966 	/* Configure the glue-logic */  in miphy28lp_init_pcie()
967 	regmap_update_bits(miphy_dev->regmap,  in miphy28lp_init_pcie()
968 			   miphy_phy->syscfg_reg[SYSCFG_SATA],  in miphy28lp_init_pcie()
971 	regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_reg[SYSCFG_PCI],  in miphy28lp_init_pcie()
978 		dev_err(miphy_dev->dev, "PCIe phy setup failed\n");  in miphy28lp_init_pcie()
988 	writeb_relaxed(0x68, miphy_phy->pipebase + 0x104); /* Rise_0 */  in miphy28lp_init_pcie()
989 	writeb_relaxed(0x61, miphy_phy->pipebase + 0x105); /* Rise_1 */  in miphy28lp_init_pcie()
990 	writeb_relaxed(0x68, miphy_phy->pipebase + 0x108); /* Fall_0 */  in miphy28lp_init_pcie()
991 	writeb_relaxed(0x61, miphy_phy->pipebase + 0x109); /* Fall-1 */  in miphy28lp_init_pcie()
992 	writeb_relaxed(0x68, miphy_phy->pipebase + 0x10c); /* Threshold_0 */  in miphy28lp_init_pcie()
993 	writeb_relaxed(0x60, miphy_phy->pipebase + 0x10d); /* Threshold_1 */  in miphy28lp_init_pcie()
1001 	struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;  in miphy28lp_init_usb3()
1004 	if ((!miphy_phy->base) || (!miphy_phy->pipebase))  in miphy28lp_init_usb3()
1005 		return -EINVAL;  in miphy28lp_init_usb3()
1007 	dev_info(miphy_dev->dev, "usb3-up mode, addr 0x%p\n", miphy_phy->base);  in miphy28lp_init_usb3()
1012 		dev_err(miphy_dev->dev, "USB3 phy setup failed\n");  in miphy28lp_init_usb3()
1020 	writeb_relaxed(0x68, miphy_phy->pipebase + 0x23);  in miphy28lp_init_usb3()
1021 	writeb_relaxed(0x61, miphy_phy->pipebase + 0x24);  in miphy28lp_init_usb3()
1022 	writeb_relaxed(0x68, miphy_phy->pipebase + 0x26);  in miphy28lp_init_usb3()
1023 	writeb_relaxed(0x61, miphy_phy->pipebase + 0x27);  in miphy28lp_init_usb3()
1024 	writeb_relaxed(0x18, miphy_phy->pipebase + 0x29);  in miphy28lp_init_usb3()
1025 	writeb_relaxed(0x61, miphy_phy->pipebase + 0x2a);  in miphy28lp_init_usb3()
1027 	/* pipe Wrapper usb3 TX swing de-emph margin PREEMPH[7:4], SWING[3:0] */  in miphy28lp_init_usb3()
1028 	writeb_relaxed(0X67, miphy_phy->pipebase + 0x68);  in miphy28lp_init_usb3()
1029 	writeb_relaxed(0x0d, miphy_phy->pipebase + 0x69);  in miphy28lp_init_usb3()
1030 	writeb_relaxed(0X67, miphy_phy->pipebase + 0x6a);  in miphy28lp_init_usb3()
1031 	writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6b);  in miphy28lp_init_usb3()
1032 	writeb_relaxed(0X67, miphy_phy->pipebase + 0x6c);  in miphy28lp_init_usb3()
1033 	writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6d);  in miphy28lp_init_usb3()
1034 	writeb_relaxed(0X67, miphy_phy->pipebase + 0x6e);  in miphy28lp_init_usb3()
1035 	writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6f);  in miphy28lp_init_usb3()
1043 	struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;  in miphy28lp_init()
1046 	mutex_lock(&miphy_dev->miphy_mutex);  in miphy28lp_init()
1048 	switch (miphy_phy->type) {  in miphy28lp_init()
1060 		ret = -EINVAL;  in miphy28lp_init()
1064 	mutex_unlock(&miphy_dev->miphy_mutex);  in miphy28lp_init()
1071 	struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;  in miphy28lp_get_addr()
1072 	struct device_node *phynode = miphy_phy->phy->dev.of_node;  in miphy28lp_get_addr()
1075 	if ((miphy_phy->type != PHY_TYPE_SATA) &&  in miphy28lp_get_addr()
1076 	    (miphy_phy->type != PHY_TYPE_PCIE) &&  in miphy28lp_get_addr()
1077 	    (miphy_phy->type != PHY_TYPE_USB3)) {  in miphy28lp_get_addr()
1078 		return -EINVAL;  in miphy28lp_get_addr()
1081 	err = miphy28lp_get_one_addr(miphy_dev->dev, phynode,  in miphy28lp_get_addr()
1082 			PHY_TYPE_name[miphy_phy->type - PHY_TYPE_SATA],  in miphy28lp_get_addr()
1083 			&miphy_phy->base);  in miphy28lp_get_addr()
1087 	if ((miphy_phy->type == PHY_TYPE_PCIE) ||  in miphy28lp_get_addr()
1088 	    (miphy_phy->type == PHY_TYPE_USB3)) {  in miphy28lp_get_addr()
1089 		err = miphy28lp_get_one_addr(miphy_dev->dev, phynode, "pipew",  in miphy28lp_get_addr()
1090 					     &miphy_phy->pipebase);  in miphy28lp_get_addr()
1103 	struct device_node *phynode = args->np;  in miphy28lp_xlate()
1106 	if (args->args_count != 1) {  in miphy28lp_xlate()
1108 		return ERR_PTR(-EINVAL);  in miphy28lp_xlate()
1111 	for (index = 0; index < miphy_dev->nphys; index++)  in miphy28lp_xlate()
1112 		if (phynode == miphy_dev->phys[index]->phy->dev.of_node) {  in miphy28lp_xlate()
1113 			miphy_phy = miphy_dev->phys[index];  in miphy28lp_xlate()
1119 		return ERR_PTR(-EINVAL);  in miphy28lp_xlate()
1122 	miphy_phy->type = args->args[0];  in miphy28lp_xlate()
1128 	return miphy_phy->phy;  in miphy28lp_xlate()
1139 	struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;  in miphy28lp_probe_resets()
1142 	miphy_phy->miphy_rst =  in miphy28lp_probe_resets()
1143 		of_reset_control_get_shared(node, "miphy-sw-rst");  in miphy28lp_probe_resets()
1145 	if (IS_ERR(miphy_phy->miphy_rst)) {  in miphy28lp_probe_resets()
1146 		dev_err(miphy_dev->dev,  in miphy28lp_probe_resets()
1148 		return PTR_ERR(miphy_phy->miphy_rst);  in miphy28lp_probe_resets()
1151 	err = reset_control_deassert(miphy_phy->miphy_rst);  in miphy28lp_probe_resets()
1153 		dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n");  in miphy28lp_probe_resets()
1166 	miphy_phy->osc_force_ext =  in miphy28lp_of_probe()
1167 		of_property_read_bool(np, "st,osc-force-ext");  in miphy28lp_of_probe()
1169 	miphy_phy->osc_rdy = of_property_read_bool(np, "st,osc-rdy");  in miphy28lp_of_probe()
1171 	miphy_phy->px_rx_pol_inv =  in miphy28lp_of_probe()
1174 	miphy_phy->ssc = of_property_read_bool(np, "st,ssc-on");  in miphy28lp_of_probe()
1176 	miphy_phy->tx_impedance =  in miphy28lp_of_probe()
1177 		of_property_read_bool(np, "st,tx-impedance-comp");  in miphy28lp_of_probe()
1179 	of_property_read_u32(np, "st,sata-gen", &miphy_phy->sata_gen);  in miphy28lp_of_probe()
1180 	if (!miphy_phy->sata_gen)  in miphy28lp_of_probe()
1181 		miphy_phy->sata_gen = SATA_GEN1;  in miphy28lp_of_probe()
1185 			miphy_phy->syscfg_reg[i] = ctrlreg;  in miphy28lp_of_probe()
1193 	struct device_node *child, *np = pdev->dev.of_node;  in miphy28lp_probe()
1199 	miphy_dev = devm_kzalloc(&pdev->dev, sizeof(*miphy_dev), GFP_KERNEL);  in miphy28lp_probe()
1201 		return -ENOMEM;  in miphy28lp_probe()
1203 	miphy_dev->nphys = of_get_child_count(np);  in miphy28lp_probe()
1204 	miphy_dev->phys = devm_kcalloc(&pdev->dev, miphy_dev->nphys,  in miphy28lp_probe()
1205 				       sizeof(*miphy_dev->phys), GFP_KERNEL);  in miphy28lp_probe()
1206 	if (!miphy_dev->phys)  in miphy28lp_probe()
1207 		return -ENOMEM;  in miphy28lp_probe()
1209 	miphy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");  in miphy28lp_probe()
1210 	if (IS_ERR(miphy_dev->regmap)) {  in miphy28lp_probe()
1211 		dev_err(miphy_dev->dev, "No syscfg phandle specified\n");  in miphy28lp_probe()
1212 		return PTR_ERR(miphy_dev->regmap);  in miphy28lp_probe()
1215 	miphy_dev->dev = &pdev->dev;  in miphy28lp_probe()
1217 	dev_set_drvdata(&pdev->dev, miphy_dev);  in miphy28lp_probe()
1219 	mutex_init(&miphy_dev->miphy_mutex);  in miphy28lp_probe()
1224 		miphy_phy = devm_kzalloc(&pdev->dev, sizeof(*miphy_phy),  in miphy28lp_probe()
1227 			ret = -ENOMEM;  in miphy28lp_probe()
1231 		miphy_dev->phys[port] = miphy_phy;  in miphy28lp_probe()
1233 		phy = devm_phy_create(&pdev->dev, child, &miphy28lp_ops);  in miphy28lp_probe()
1235 			dev_err(&pdev->dev, "failed to create PHY\n");  in miphy28lp_probe()
1240 		miphy_dev->phys[port]->phy = phy;  in miphy28lp_probe()
1241 		miphy_dev->phys[port]->phydev = miphy_dev;  in miphy28lp_probe()
1247 		ret = miphy28lp_probe_resets(child, miphy_dev->phys[port]);  in miphy28lp_probe()
1251 		phy_set_drvdata(phy, miphy_dev->phys[port]);  in miphy28lp_probe()
1256 	provider = devm_of_phy_provider_register(&pdev->dev, miphy28lp_xlate);  in miphy28lp_probe()
1264 	{.compatible = "st,miphy28lp-phy", },
1273 		.name = "miphy28lp-phy",