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/Linux-v6.1/Documentation/devicetree/bindings/fpga/
Dfpga-region.txt1 FPGA Region Device Tree Binding
9 - FPGA Region
18 FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in
19 the Device Tree. FPGA Regions provide a way to program FPGAs under device tree
22 This device tree binding document hits some of the high points of FPGA usage and
23 attempts to include terminology used by both major FPGA manufacturers. This
24 document isn't a replacement for any manufacturers specifications for FPGA
32 * The entire FPGA is programmed.
35 * A section of an FPGA is reprogrammed while the rest of the FPGA is not
37 * Not all FPGA's support PR.
[all …]
Dxilinx-slave-serial.txt1 Xilinx Slave Serial SPI FPGA Manager
11 - https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
14 - compatible: should contain "xlnx,fpga-slave-serial"
15 - reg: spi chip select of the FPGA
23 Example for full FPGA configuration:
25 fpga-region0 {
26 compatible = "fpga-region";
27 fpga-mgr = <&fpga_mgr_spi>;
42 fpga_mgr_spi: fpga-mgr@0 {
43 compatible = "xlnx,fpga-slave-serial";
/Linux-v6.1/drivers/fpga/
DKconfig3 # FPGA framework configuration
6 menuconfig FPGA config
7 tristate "FPGA Configuration Framework"
10 kernel. The FPGA framework adds an FPGA manager class and FPGA
13 if FPGA
16 tristate "Altera SOCFPGA FPGA Manager"
19 FPGA manager driver support for Altera SOCFPGA.
26 FPGA manager driver support for Altera Arria10 SoCFPGA.
41 tristate "Altera FPGA Passive Serial over SPI"
45 FPGA manager driver support for Altera Arria/Cyclone/Stratix
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Dof-fpga-region.c3 * FPGA Region - Device Tree support for FPGA programming under Linux
8 #include <linux/fpga/fpga-bridge.h>
9 #include <linux/fpga/fpga-mgr.h>
10 #include <linux/fpga/fpga-region.h>
20 { .compatible = "fpga-region", },
26 * of_fpga_region_find - find FPGA region
27 * @np: device node of FPGA Region
31 * Return: FPGA Region struct or NULL
39 * of_fpga_region_get_mgr - get reference for FPGA manager
40 * @np: device node of FPGA region
[all …]
Dfpga-mgr.c3 * FPGA Manager Core
12 #include <linux/fpga/fpga-mgr.h>
56 * After all the FPGA image has been written, do the device specific steps to
57 * finish and set the FPGA into operating mode.
68 dev_err(&mgr->dev, "Error after writing image data to FPGA\n"); in fpga_mgr_write_complete()
104 * fpga_image_info_alloc - Allocate an FPGA image info struct
128 * fpga_image_info_free - Free an FPGA image info struct
129 * @info: FPGA image info struct to free
148 * Call the low level driver's parse_header function with entire FPGA image
161 dev_err(&mgr->dev, "Bitstream data outruns FPGA image\n"); in fpga_mgr_parse_header_mapped()
[all …]
Dfpga-region.c3 * FPGA Region - Support for FPGA programming under Linux
8 #include <linux/fpga/fpga-bridge.h>
9 #include <linux/fpga/fpga-mgr.h>
10 #include <linux/fpga/fpga-region.h>
36 * fpga_region_get - get an exclusive reference to an fpga region
37 * @region: FPGA Region struct
43 * Return -ENODEV if @np is not an FPGA Region.
50 dev_dbg(dev, "%s: FPGA Region already in use\n", __func__); in fpga_region_get()
69 * @region: FPGA region
83 * fpga_region_program_fpga - program FPGA
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Dfpga-bridge.c3 * FPGA Bridge Framework Driver
8 #include <linux/fpga/fpga-bridge.h>
25 * @bridge: FPGA bridge
43 * @bridge: FPGA bridge
88 * of_fpga_bridge_get - get an exclusive reference to an fpga bridge
90 * @np: node pointer of an FPGA bridge
91 * @info: fpga image specific information
95 * Return -ENODEV if @np is not an FPGA Bridge.
116 * fpga_bridge_get - get an exclusive reference to an fpga bridge
117 * @dev: parent device that fpga bridge was registered with
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DMakefile3 # Makefile for the fpga framework and fpga manager drivers.
6 # Core FPGA Manager Framework
7 obj-$(CONFIG_FPGA) += fpga-mgr.o
9 # FPGA Manager Drivers
17 obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
19 obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
20 obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o
21 obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o
26 # FPGA Secure Update Drivers
29 # FPGA Bridge Drivers
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/Linux-v6.1/Documentation/driver-api/fpga/
Dfpga-region.rst1 FPGA Region
7 This document is meant to be a brief overview of the FPGA region API usage. A
12 an FPGA Manager and a bridge (or bridges) with a reprogrammable region of an
13 FPGA or the whole FPGA. The API provides a way to register a region and to
16 Currently the only layer above fpga-region.c in the kernel is the Device Tree
17 support (of-fpga-region.c) described in [#f1]_. The DT support layer uses regions
18 to program the FPGA and then DT to handle enumeration. The common region code
22 An fpga-region can be set up to know the following things:
24 * which FPGA manager to use to do the programming
28 Additional info needed to program the FPGA image is passed in the struct
[all …]
Dfpga-programming.rst1 In-kernel API for FPGA Programming
7 The in-kernel API for FPGA programming is a combination of APIs from
8 FPGA manager, bridge, and regions. The actual function used to
9 trigger FPGA programming is fpga_region_program_fpga().
12 the FPGA manager and bridges. It will:
15 * lock the mutex of the region's FPGA manager
16 * build a list of FPGA bridges if a method has been specified to do so
18 * program the FPGA using info passed in :c:expr:`fpga_region->info`.
22 The struct fpga_image_info specifies what FPGA image to program. It is
26 How to program an FPGA using a region
[all …]
Dintro.rst4 The FPGA subsystem supports reprogramming FPGAs dynamically under
5 Linux. Some of the core intentions of the FPGA subsystems are:
7 * The FPGA subsystem is vendor agnostic.
9 * The FPGA subsystem separates upper layers (userspace interfaces and
11 FPGA.
16 other users. Write the linux-fpga mailing list and maintainers and
23 FPGA Manager
26 If you are adding a new FPGA or a new method of programming an FPGA,
27 this is the subsystem for you. Low level FPGA manager drivers contain
29 includes the framework in fpga-mgr.c and the low level drivers that
[all …]
Dfpga-mgr.rst1 FPGA Manager
7 The FPGA manager core exports a set of functions for programming an FPGA with
10 The FPGA image data itself is very manufacturer specific, but for our purposes
11 it's just binary data. The FPGA manager core won't parse it.
13 The FPGA image to be programmed can be in a scatter gather list, a single
20 FPGA image as well as image-specific particulars such as whether the image was
23 How to support a new FPGA device
26 To add another FPGA manager, write a driver that implements a set of ops. The
52 mgr = fpga_mgr_register(dev, "Altera SOCFPGA FPGA Manager",
78 do the programming sequence for this particular FPGA. These ops return 0 for
[all …]
Dfpga-bridge.rst1 FPGA Bridge
4 API to implement a new FPGA bridge
7 * struct fpga_bridge - The FPGA Bridge structure
12 .. kernel-doc:: include/linux/fpga/fpga-bridge.h
15 .. kernel-doc:: include/linux/fpga/fpga-bridge.h
18 .. kernel-doc:: drivers/fpga/fpga-bridge.c
21 .. kernel-doc:: drivers/fpga/fpga-bridge.c
/Linux-v6.1/arch/arm/mach-pxa/
Dpxa_cplds_irqs.c36 struct cplds *fpga = d; in cplds_irq_handler() local
41 pending = readl(fpga->base + FPGA_IRQ_SET_CLR) & fpga->irq_mask; in cplds_irq_handler()
43 generic_handle_domain_irq(fpga->irqdomain, bit); in cplds_irq_handler()
51 struct cplds *fpga = irq_data_get_irq_chip_data(d); in cplds_irq_mask() local
55 fpga->irq_mask &= ~bit; in cplds_irq_mask()
56 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); in cplds_irq_mask()
61 struct cplds *fpga = irq_data_get_irq_chip_data(d); in cplds_irq_unmask() local
65 set = readl(fpga->base + FPGA_IRQ_SET_CLR); in cplds_irq_unmask()
66 writel(set & ~bit, fpga->base + FPGA_IRQ_SET_CLR); in cplds_irq_unmask()
68 fpga->irq_mask |= bit; in cplds_irq_unmask()
[all …]
/Linux-v6.1/include/linux/fpga/
Dfpga-mgr.h3 * FPGA Framework
18 * enum fpga_mgr_states - fpga framework states
20 * @FPGA_MGR_STATE_POWER_OFF: FPGA power is off
21 * @FPGA_MGR_STATE_POWER_UP: FPGA reports power is up
22 * @FPGA_MGR_STATE_RESET: FPGA in reset state
25 * @FPGA_MGR_STATE_PARSE_HEADER: parse FPGA image header
27 * @FPGA_MGR_STATE_WRITE_INIT: preparing FPGA for programming
29 * @FPGA_MGR_STATE_WRITE: writing image to FPGA
30 * @FPGA_MGR_STATE_WRITE_ERR: Error while writing FPGA
33 * @FPGA_MGR_STATE_OPERATING: FPGA is programmed and operating
[all …]
Dfpga-bridge.h7 #include <linux/fpga/fpga-mgr.h>
12 * struct fpga_bridge_ops - ops for low level FPGA bridge drivers
13 * @enable_show: returns the FPGA bridge's status
14 * @enable_set: set an FPGA bridge as enabled or disabled
15 * @fpga_bridge_remove: set FPGA into a specific state during driver remove
26 * struct fpga_bridge_info - collection of parameters an FPGA Bridge
27 * @name: fpga bridge name
28 * @br_ops: pointer to structure of fpga bridge ops
29 * @priv: fpga bridge private data
43 * struct fpga_bridge - FPGA bridge structure
[all …]
Dfpga-region.h7 #include <linux/fpga/fpga-mgr.h>
8 #include <linux/fpga/fpga-bridge.h>
13 * struct fpga_region_info - collection of parameters an FPGA Region
14 * @mgr: fpga region manager
15 * @compat_id: FPGA region id for compatibility check.
16 * @priv: fpga region private data
32 * struct fpga_region - FPGA Region structure
33 * @dev: FPGA Region device
35 * @bridge_list: list of FPGA bridges specified in region
36 * @mgr: FPGA manager
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/board/
Dfsl-board.txt20 * Freescale on-board FPGA
22 This is the memory-mapped registers for on board FPGA.
26 indicating the type of FPGA. Example:
27 "fsl,<board>-fpga", "fsl,fpga-pixis", or
28 "fsl,<board>-fpga", "fsl,fpga-qixis"
29 - reg: should contain the address and the length of the FPGA register set.
37 compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
46 compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis";
50 * Freescale on-board FPGA connected on I2C bus
52 Some Freescale boards like BSC9132QDS have on board FPGA connected on
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/Linux-v6.1/Documentation/ABI/testing/
Dsysfs-class-fpga-manager1 What: /sys/class/fpga_manager/<fpga>/name
5 Description: Name of low level fpga manager driver.
7 What: /sys/class/fpga_manager/<fpga>/state
11 Description: Read fpga manager state as a string.
13 wrong during FPGA programming (something that the driver can't
18 This is a superset of FPGA states and fpga manager driver
19 states. The fpga manager driver is walking through these steps
20 to get the FPGA into a known operating state. It's a sequence,
21 though some steps may get skipped. Valid FPGA states will vary
25 * power off = FPGA power is off
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/Linux-v6.1/Documentation/driver-api/
Dxillybus.rst2 Xillybus driver for generic FPGA interface
22 -- Host never reads from the FPGA
37 An FPGA (Field Programmable Gate Array) is a piece of logic hardware, which
48 level, even lower than assembly language. In order to allow FPGA designers to
51 FPGA parallels of library functions. IP cores may implement certain
57 One of the daunting tasks in FPGA design is communicating with a fullblown
60 (registers, interrupts, DMA etc.) is a project in itself. When the FPGA's
62 make sense to design the FPGA's interface logic specifically for the project.
63 A special driver is then written to present the FPGA as a well-known interface
65 FPGA differently than any device on the bus.
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/Linux-v6.1/Documentation/fpga/
Ddfl.rst2 FPGA Device Feature List (DFL) Framework Overview
12 The Device Feature List (DFL) FPGA framework (and drivers according to
15 configure, enumerate, open and access FPGA accelerators on platforms which
17 enables system level management functions such as FPGA reconfiguration.
24 walk through these predefined data structures to enumerate FPGA features:
25 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
56 FPGA Interface Unit (FIU) represents a standalone functional unit for the
57 interface to FPGA, e.g. the FPGA Management Engine (FME) and Port (more
60 Accelerated Function Unit (AFU) represents an FPGA programmable region and
75 and can be implemented in register regions of any FPGA device.
[all …]
/Linux-v6.1/drivers/net/ethernet/mellanox/mlx5/core/fpga/
Dsdk.h42 * This header defines the in-kernel API for Innova FPGA client drivers.
51 * @MLX5_FPGA_ACCESS_TYPE_I2C: Use the slow CX-FPGA I2C bus
87 * @conn: FPGA Connection this packet was sent to
88 * @fdev: FPGA device this packet was sent to
98 * struct mlx5_fpga_conn_attr - FPGA connection attributes
122 * mlx5_fpga_sbu_conn_create() - Initialize a new FPGA SBU connection
123 * @fdev: The FPGA device
126 * Sets up a new FPGA SBU connection with the specified attributes.
140 * mlx5_fpga_sbu_conn_destroy() - Destroy an FPGA SBU connection
141 * @conn: The FPGA SBU connection to destroy
[all …]
/Linux-v6.1/drivers/watchdog/
Dpika_wdt.c3 * PIKA FPGA based Watchdog Timer
50 void __iomem *fpga; member
71 /* -- FPGA: Reset Control Register (32bit R/W) (Offset: 0x14) -- in pikawdt_reset()
80 unsigned reset = in_be32(pikawdt_private.fpga + 0x14); in pikawdt_reset()
83 out_be32(pikawdt_private.fpga + 0x14, reset); in pikawdt_reset()
229 void __iomem *fpga; in pikawdt_init() local
233 np = of_find_compatible_node(NULL, NULL, "pika,fpga"); in pikawdt_init()
235 pr_err("Unable to find fpga\n"); in pikawdt_init()
239 pikawdt_private.fpga = of_iomap(np, 0); in pikawdt_init()
241 if (pikawdt_private.fpga == NULL) { in pikawdt_init()
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/Linux-v6.1/arch/arm/mach-omap1/
Dfpga.c3 * linux/arch/arm/mach-omap1/fpga.c
5 * Interrupt handler for OMAP-1510 Innovator FPGA
12 * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
30 #include "fpga.h"
62 /* Don't need to explicitly ACK FPGA interrupts */ in fpga_ack_irq()
106 .name = "FPGA-ack",
114 .name = "FPGA",
121 * All of the FPGA interrupt request inputs except for the touchscreen are
124 * status register from the FPGA. The edge-sensitive interrupt inputs
127 * interrupt input is masked in the FPGA, which results in a missed
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/Linux-v6.1/arch/sh/include/mach-common/mach/
Dmicrodev.h17 * controller (INTC) on the CPU-board FPGA. should be noted that there
18 * is an INTC on the FPGA, and a separate INTC on the SH4-202 core -
23 #define MICRODEV_FPGA_INTC_BASE 0xa6110000ul /* INTC base address on CPU-board FPGA */
24 …INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */
25 …NTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */
26 …RODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interrupt mask to enable/disable INTC in CPU-board FPGA */
27 …(MICRODEV_FPGA_INTC_BASE+0x10+((n)/8)*8)/* Interrupt Priority Register on INTC on CPU-board FPGA */
29 …(n) (MICRODEV_FPGA_INTPRI_LEVEL((n),0xful)) /* Interrupt Priority Mask on INTC on CPU-board FPGA */
30 …TSRC_REG (MICRODEV_FPGA_INTC_BASE+0x30ul) /* Interrupt Source Register on INTC on CPU-board FPGA */
31 …REQ_REG (MICRODEV_FPGA_INTC_BASE+0x38ul) /* Interrupt Request Register on INTC on CPU-board FPGA */
[all …]

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