Lines Matching full:fpga
2 FPGA Device Feature List (DFL) Framework Overview
12 The Device Feature List (DFL) FPGA framework (and drivers according to
15 configure, enumerate, open and access FPGA accelerators on platforms which
17 enables system level management functions such as FPGA reconfiguration.
24 walk through these predefined data structures to enumerate FPGA features:
25 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
56 FPGA Interface Unit (FIU) represents a standalone functional unit for the
57 interface to FPGA, e.g. the FPGA Management Engine (FME) and Port (more
60 Accelerated Function Unit (AFU) represents an FPGA programmable region and
75 and can be implemented in register regions of any FPGA device.
78 FIU - FME (FPGA Management Engine)
80 The FPGA Management Engine performs reconfiguration and other infrastructure
81 functions. Each FPGA device only has one FME.
100 bitstream_id indicates version of the static FPGA region.
103 bitstream_metadata includes detailed information of static FPGA region,
107 one FPGA device may have more than one port, this sysfs interface indicates
108 how many ports the FPGA device has.
132 A port represents the interface between the static FPGA fabric and a partially
134 to the accelerator and exposes features such as reset and debug. Each FPGA
161 reset the FPGA Port and its AFU. Userspace can do Port
189 | FPGA Container Device | Device Feature List
190 | (FPGA Base Region) | Framework
194 | FPGA DFL Device Module |
198 | FPGA Hardware Device |
202 (FPGA base region), discover feature devices and their private features from the
208 The FPGA DFL Device could be different hardware, e.g. PCIe device, platform
213 (Please refer to drivers/fpga/dfl.c for detailed enumeration APIs).
215 The FPGA Management Engine (FME) driver is a platform driver which is loaded
217 provides the key features for FPGA management, including:
219 a) Expose static FPGA region information, e.g. version and metadata.
223 b) Partial Reconfiguration. The FME driver creates FPGA manager, FPGA
224 bridges and FPGA regions during PR sub feature initialization. Once
226 common interface function from FPGA Region to complete the partial
229 Similar to the FME driver, the FPGA Accelerated Function Unit (AFU) driver is
245 generated for the exact static FPGA region and targeted reconfigurable region
246 (port) of the FPGA, otherwise, the reconfiguration operation will fail and
249 the compat_id exposed by the target FPGA region. This check is usually done by
253 FPGA virtualization - PCIe SRIOV
255 This section describes the virtualization support on DFL based FPGA device to
257 (VM). This section only describes the PCIe based FPGA device with SRIOV support.
259 Features supported by the particular FPGA device are exposed through Device
280 | DFL based FPGA PCIe Device |
295 | FPGA || FPGA || FPGA | |
303 | FPGA Container Device | | | FPGA Container Device |
304 | (FPGA Base Region) | | | (FPGA Base Region) |
307 | FPGA PCIE Module | | Virtual | FPGA PCIE Module |
314 FPGA PCIe device driver is always loaded first once an FPGA PCIe PF or VF device
317 * Finishes enumeration on both FPGA PCIe PF and VF device using common
350 This section introduces how applications enumerate the fpga device from
353 In the example below, two DFL based FPGA devices are installed in the host. Each
354 fpga device has one FME and two ports (AFUs).
356 FPGA regions are created under /sys/class/fpga_region/::
365 fpga region which represents the FPGA device.
399 FPGA cache hit/miss rate, transaction number, interface clock counter of AFU
400 and other FPGA performance events.
402 Different FPGA devices may have different counter sets, depending on hardware
403 implementation. E.g., some discrete FPGA cards don't have any cache. User could
414 category; "portid" is introduced to decide counters set to monitor on FPGA
467 since they are system-wide counters on FPGA device.
502 FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)
542 The purpose of an FPGA is to be reprogrammed with newly developed hardware