| /Linux-v5.15/drivers/memory/tegra/ |
| D | tegra30-emc.c | 5 * Based on downstream driver from NVIDIA and tegra124-emc.c
374 * There are multiple sources in the EMC driver which could request
383 static int emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
388 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
390 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()
394 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()
403 struct tegra_emc *emc = data; in tegra_emc_isr() local
407 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
413 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
417 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
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| D | tegra20-emc.c | 195 * There are multiple sources in the EMC driver which could request
208 struct tegra_emc *emc = data; in tegra_emc_isr() local
212 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
218 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
222 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
227 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, in tegra_emc_find_timing() argument
233 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing()
234 if (emc->timings[i].rate >= rate) { in tegra_emc_find_timing()
235 timing = &emc->timings[i]; in tegra_emc_find_timing()
241 dev_err(emc->dev, "no timing for rate %lu\n", rate); in tegra_emc_find_timing()
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| D | tegra210-emc-core.c | 21 #include "tegra210-emc.h"
69 next->trim_perch_regs[EMC ## chan ## \
561 struct tegra210_emc *emc = from_timer(emc, timer, training); in tegra210_emc_train() local
564 if (!emc->last) in tegra210_emc_train()
567 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_train()
569 if (emc->sequence->periodic_compensation) in tegra210_emc_train()
570 emc->sequence->periodic_compensation(emc); in tegra210_emc_train()
572 spin_unlock_irqrestore(&emc->lock, flags); in tegra210_emc_train()
574 mod_timer(&emc->training, in tegra210_emc_train()
575 jiffies + msecs_to_jiffies(emc->training_interval)); in tegra210_emc_train()
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| D | tegra186-emc.c | 38 * to control the EMC frequency. The top-level directory can be found here:
40 * /sys/kernel/debug/emc
45 * EMC frequencies.
49 * configured EMC frequency, this will cause the frequency to be
54 * the value is lower than the currently configured EMC frequency, this
59 static bool tegra186_emc_validate_rate(struct tegra186_emc *emc, in tegra186_emc_validate_rate() argument
64 for (i = 0; i < emc->num_dvfs; i++) in tegra186_emc_validate_rate()
65 if (rate == emc->dvfs[i].rate) in tegra186_emc_validate_rate()
74 struct tegra186_emc *emc = s->private; in tegra186_emc_debug_available_rates_show() local
78 for (i = 0; i < emc->num_dvfs; i++) { in tegra186_emc_debug_available_rates_show()
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| D | tegra124-emc.c | 507 * There are multiple sources in the EMC driver which could request
518 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, in emc_ccfifo_writel() argument
521 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
522 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
525 static void emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
530 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
533 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing()
539 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
542 static void emc_seq_disable_auto_cal(struct tegra_emc *emc) in emc_seq_disable_auto_cal() argument
547 writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_seq_disable_auto_cal()
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| D | tegra210-emc-cc-r21021.c | 14 #include "tegra210-emc.h"
36 #define emc_dbg(emc, flags, ...) dev_dbg(emc->dev, __VA_ARGS__) argument
108 emc_dbg(emc, EMA_UPDATES, "%s: (s=%lu) EMA: %u\n", \
116 static u32 update_clock_tree_delay(struct tegra210_emc *emc, int type) in update_clock_tree_delay() argument
119 struct tegra210_emc_timing *last = emc->last; in update_clock_tree_delay()
120 struct tegra210_emc_timing *next = emc->next; in update_clock_tree_delay()
134 value = tegra210_emc_mrr_read(emc, 2, 19); in update_clock_tree_delay()
136 for (i = 0; i < emc->num_channels; i++) { in update_clock_tree_delay()
145 value = tegra210_emc_mrr_read(emc, 2, 18); in update_clock_tree_delay()
147 for (i = 0; i < emc->num_channels; i++) { in update_clock_tree_delay()
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| D | tegra210-emc-table.c | 8 #include "tegra210-emc.h"
15 struct tegra210_emc *emc = dev_get_drvdata(dev); in tegra210_emc_table_device_init() local
21 dev_err(dev, "failed to map EMC table\n"); in tegra210_emc_table_device_init()
35 if (emc->derated) { in tegra210_emc_table_device_init()
36 dev_warn(dev, "excess EMC table '%s'\n", rmem->name); in tegra210_emc_table_device_init()
40 if (emc->nominal) { in tegra210_emc_table_device_init()
41 if (count != emc->num_timings) { in tegra210_emc_table_device_init()
43 count, emc->num_timings); in tegra210_emc_table_device_init()
48 emc->derated = timings; in tegra210_emc_table_device_init()
50 emc->num_timings = count; in tegra210_emc_table_device_init()
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| D | Makefile | 15 obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o
16 obj-$(CONFIG_TEGRA30_EMC) += tegra30-emc.o
17 obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o
18 obj-$(CONFIG_TEGRA210_EMC_TABLE) += tegra210-emc-table.o
19 obj-$(CONFIG_TEGRA210_EMC) += tegra210-emc.o
20 obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-emc.o
21 obj-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186-emc.o
23 tegra210-emc-y := tegra210-emc-core.o tegra210-emc-cc-r21021.o
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| D | Kconfig | 20 This driver is for the External Memory Controller (EMC) found on
21 Tegra20 chips. The EMC controls the external DRAM on the board.
31 This driver is for the External Memory Controller (EMC) found on
32 Tegra30 chips. The EMC controls the external DRAM on the board.
43 This driver is for the External Memory Controller (EMC) found on
44 Tegra124 chips. The EMC controls the external DRAM on the board.
57 This driver is for the External Memory Controller (EMC) found on
58 Tegra210 chips. The EMC controls the external DRAM on the board.
|
| D | tegra210-emc.h | 891 /* nominal EMC frequency table */
893 /* derated EMC frequency table */
939 void (*set_clock)(struct tegra210_emc *emc, u32 clksrc);
940 u32 (*periodic_compensation)(struct tegra210_emc *emc);
943 static inline void emc_writel(struct tegra210_emc *emc, u32 value, in emc_writel() argument
946 writel_relaxed(value, emc->regs + offset); in emc_writel()
949 static inline u32 emc_readl(struct tegra210_emc *emc, unsigned int offset) in emc_readl() argument
951 return readl_relaxed(emc->regs + offset); in emc_readl()
954 static inline void emc_channel_writel(struct tegra210_emc *emc, in emc_channel_writel() argument
958 writel_relaxed(value, emc->channel[channel] + offset); in emc_channel_writel()
[all …]
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| /Linux-v5.15/arch/arm/boot/dts/ |
| D | tegra124-nyan-blaze-emc.dtsi | 4 emc-timings-1 {
11 clock-names = "emc-parent";
17 clock-names = "emc-parent";
23 clock-names = "emc-parent";
29 clock-names = "emc-parent";
35 clock-names = "emc-parent";
41 clock-names = "emc-parent";
47 clock-names = "emc-parent";
53 clock-names = "emc-parent";
60 clock-names = "emc-parent";
[all …]
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| D | tegra124-jetson-tk1-emc.dtsi | 4 emc-timings-3 {
11 clock-names = "emc-parent";
17 clock-names = "emc-parent";
23 clock-names = "emc-parent";
29 clock-names = "emc-parent";
35 clock-names = "emc-parent";
41 clock-names = "emc-parent";
47 clock-names = "emc-parent";
53 clock-names = "emc-parent";
59 clock-names = "emc-parent";
[all …]
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| D | tegra124-apalis-emc.dtsi | 9 emc-timings-1 {
16 clock-names = "emc-parent";
22 clock-names = "emc-parent";
28 clock-names = "emc-parent";
34 clock-names = "emc-parent";
40 clock-names = "emc-parent";
46 clock-names = "emc-parent";
52 clock-names = "emc-parent";
58 clock-names = "emc-parent";
64 clock-names = "emc-parent";
[all …]
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| D | tegra124-nyan-big-emc.dtsi | 8 emc-timings-1 {
15 clock-names = "emc-parent";
21 clock-names = "emc-parent";
27 clock-names = "emc-parent";
33 clock-names = "emc-parent";
39 clock-names = "emc-parent";
45 clock-names = "emc-parent";
51 clock-names = "emc-parent";
57 clock-names = "emc-parent";
63 clock-names = "emc-parent";
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| D | tegra30-asus-nexus7-grouper-memory-timings.dtsi | 5 emc-timings-0 {
159 emc-timings-1 {
315 emc-timings-0 {
321 nvidia,emc-auto-cal-interval = <0x001fffff>;
322 nvidia,emc-mode-1 = <0x80100003>;
323 nvidia,emc-mode-2 = <0x80200008>;
324 nvidia,emc-mode-reset = <0x80001221>;
325 nvidia,emc-zcal-cnt-long = <0x00000040>;
326 nvidia,emc-cfg-dyn-self-ref;
327 nvidia,emc-cfg-periodic-qrst;
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| D | tegra30-asus-nexus7-tilapia-memory-timings.dtsi | 13 emc-timings-0 {
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
19 nvidia,emc-mode-2 = <0x80200018>;
20 nvidia,emc-mode-reset = <0x80000b71>;
21 nvidia,emc-zcal-cnt-long = <0x00000040>;
22 nvidia,emc-cfg-periodic-qrst;
24 nvidia,emc-configuration = <
118 emc-timings-1 {
122 nvidia,emc-auto-cal-interval = <0x001fffff>;
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| D | tegra20-acer-a500-picasso.dts | 1111 emc-tables@0 {
1118 emc-table@25000 {
1120 compatible = "nvidia,tegra20-emc-table";
1122 nvidia,emc-registers = <0x00000002 0x00000006
1136 emc-table@50000 {
1138 compatible = "nvidia,tegra20-emc-table";
1140 nvidia,emc-registers = <0x00000003 0x00000007
1154 emc-table@75000 {
1156 compatible = "nvidia,tegra20-emc-table";
1158 nvidia,emc-registers = <0x00000005 0x0000000a
[all …]
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| /Linux-v5.15/drivers/clk/tegra/ |
| D | clk-tegra20-emc.c | 3 * Based on drivers/clk/tegra/clk-emc.c
10 #define pr_fmt(fmt) "tegra-emc-clk: " fmt
57 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw); in emc_recalc_rate() local
60 val = readl_relaxed(emc->reg); in emc_recalc_rate()
68 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw); in emc_get_parent() local
70 return readl_relaxed(emc->reg) >> CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT; in emc_get_parent()
75 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw); in emc_set_parent() local
78 val = readl_relaxed(emc->reg); in emc_set_parent()
84 if (index == EMC_SRC_PLL_M && div == 0 && emc->want_low_jitter) in emc_set_parent()
89 if (emc->mc_same_freq) in emc_set_parent()
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| D | clk-tegra210-emc.c | 53 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_get_parent() local
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
66 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_recalc_rate() local
74 * This can lead to wrong results being reported for the EMC clock if in tegra210_clk_emc_recalc_rate()
75 * the parent and/or parent rate have changed as part of the EMC rate in tegra210_clk_emc_recalc_rate()
81 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_recalc_rate()
92 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_round_rate() local
93 struct tegra210_clk_emc_provider *provider = emc->provider; in tegra210_clk_emc_round_rate()
107 static struct clk *tegra210_clk_emc_find_parent(struct tegra210_clk_emc *emc, in tegra210_clk_emc_find_parent() argument
110 struct clk_hw *parent = clk_hw_get_parent_by_index(&emc->hw, index); in tegra210_clk_emc_find_parent()
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| D | clk-tegra124-emc.c | 3 * drivers/clk/tegra/clk-emc.c
47 * List of clock sources for various parents the EMC clock can have.
79 struct tegra_emc *emc; member
113 * safer since things have EMC rate floors. Also don't touch parent_rate
180 if (tegra->emc) in emc_ensure_emc_driver()
181 return tegra->emc; in emc_ensure_emc_driver()
199 tegra->emc = platform_get_drvdata(pdev); in emc_ensure_emc_driver()
200 if (!tegra->emc) { in emc_ensure_emc_driver()
201 pr_err("%s: cannot find EMC driver\n", __func__); in emc_ensure_emc_driver()
205 return tegra->emc; in emc_ensure_emc_driver()
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| /Linux-v5.15/Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra124-emc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra124-emc
30 - const: emc
51 "^emc-timings-[0-9]+$":
70 nvidia,emc-auto-cal-config:
76 nvidia,emc-auto-cal-config2:
82 nvidia,emc-auto-cal-config3:
88 nvidia,emc-auto-cal-interval:
95 nvidia,emc-bgbias-ctl0:
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| D | nvidia,tegra30-emc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
23 const: nvidia,tegra30-emc
53 "^emc-timings-[0-9]+$":
71 nvidia,emc-auto-cal-interval:
78 nvidia,emc-mode-1:
83 nvidia,emc-mode-2:
88 nvidia,emc-mode-reset:
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| D | nvidia,tegra20-emc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
16 service the request stream sent from Memory Controller. The EMC also has
18 parameters and initialization settings. Tegra20 EMC supports multiple JEDEC
23 const: nvidia,tegra20-emc
61 If present, the emc-tables@ sub-nodes will be addressed.
64 emc-table:
68 const: nvidia,tegra20-emc-table
82 nvidia,emc-registers:
84 EMC timing characterization data. These are the registers
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| D | nvidia,tegra210-emc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml#
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra210-emc
30 - const: emc
34 - description: EMC general interrupt
39 phandle to a reserved memory region describing the table of EMC
66 emc_table: emc-table@83400000 {
67 compatible = "nvidia,tegra210-emc-table";
73 compatible = "nvidia,tegra210-emc";
78 clock-names = "emc";
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| /Linux-v5.15/drivers/pinctrl/ |
| D | pinctrl-lpc18xx.c | 140 [FUNC_EMC] = "emc",
240 LPC_P(1,0, GPIO, CTIN, EMC, R, R, SSP0, SGPIO, R, 0, ND);
241 LPC_P(1,1, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND);
242 LPC_P(1,2, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND);
243 LPC_P(1,3, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
244 LPC_P(1,4, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
245 LPC_P(1,5, GPIO, CTOUT, R, EMC, USB0, SSP1, SGPIO, SDMMC, 0, ND);
246 LPC_P(1,6, GPIO, CTIN, R, EMC, R, R, SGPIO, SDMMC, 0, ND);
247 LPC_P(1,7, GPIO, UART1, CTOUT, EMC, USB0, R, R, R, 0, ND);
248 LPC_P(1,8, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
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