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/Linux-v5.15/Documentation/devicetree/bindings/clock/ti/
Ddpll.txt1 Binding for Texas Instruments DPLL clock.
6 register-mapped DPLL with usually two selectable input clocks
12 for the actual DPLL clock.
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
22 "ti,omap4-dpll-clock",
23 "ti,omap4-dpll-x2-clock",
24 "ti,omap4-dpll-core-clock",
[all …]
/Linux-v5.15/drivers/clk/ti/
Ddpll3xxx.c3 * OMAP3/4 - specific DPLL control functions
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
60 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
129 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
130 * @clk: pointer to a DPLL struct clk
132 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
133 * readiness before returning. Will save and restore the DPLL's
134 * autoidle state across the enable, per the CDP code. If the DPLL
135 * locked successfully, return 0; if the DPLL did not lock in the time
145 pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_lock()
[all …]
Dclkt_dpll.c3 * OMAP2/3/4 DPLL clock functions
25 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
33 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
44 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
45 * From device data manual section 4.3 "DPLL and DLL Specifications".
57 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
58 * @clk: DPLL struct clk to test
61 * Tests whether a particular divider @n will result in a valid DPLL
62 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
75 /* DPLL divider must result in a valid jitter correction val */ in _dpll_test_fint()
[all …]
Ddpll44xx.c3 * OMAP4-specific DPLL control functions
19 * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
20 * can supported when using the DPLL low-power mode. Frequencies are
79 * omap4_dpll_lpmode_recalc - compute DPLL low-power setting
80 * @dd: pointer to the dpll data structure
104 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
106 * @parent_rate: clock rate of the DPLL parent
108 * Compute the output rate for the OMAP4 DPLL represented by @clk.
110 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
128 /* regm4xen adds a multiplier of 4 to DPLL calculations */ in omap4_dpll_regm4xen_recalc()
[all …]
Ddpll.c2 * OMAP DPLL clock support
153 * _register_dpll - low level registration of a DPLL clock
157 * Finalizes DPLL registration process. In case a failure (clk-ref or
221 * Initializes a DPLL x 2 clock from device tree data.
278 * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
279 * @node: device node containing the DPLL info
280 * @ops: ops for the DPLL
281 * @ddt: DPLL data template to use
283 * Initializes a DPLL clock from device tree data.
328 * Special case for OMAP2 DPLL, register order is different due to in of_ti_dpll_setup()
[all …]
/Linux-v5.15/drivers/gpu/drm/i915/display/
Dintel_dpll.c300 int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params()
312 static u32 i9xx_dpll_compute_m(struct dpll *dpll) in i9xx_dpll_compute_m() argument
314 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
317 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params()
329 int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params()
341 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params()
360 const struct dpll *clock) in intel_pll_is_valid()
431 int target, int refclk, struct dpll *match_clock, in i9xx_find_best_dpll()
432 struct dpll *best_clock) in i9xx_find_best_dpll()
435 struct dpll clock; in i9xx_find_best_dpll()
[all …]
Dintel_dpll.h11 struct dpll;
18 int vlv_calc_dpll_params(int refclk, struct dpll *clock);
19 int pnv_calc_dpll_params(int refclk, struct dpll *clock);
20 int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
27 const struct dpll *dpll);
43 struct dpll *best_clock);
44 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
Dintel_dpll_mgr.h49 * enum intel_dpll_id - possible DPLL ids
51 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.
55 * @DPLL_ID_PRIVATE: non-shared dpll in use
60 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB
64 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB
187 u32 dpll; member
198 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
201 * the DPLL.
232 * struct intel_shared_dpll_state - hold the DPLL atomic state
234 * This structure holds an atomic state for the DPLL, that can represent
[all …]
Dintel_dpll_mgr.c72 /* Copy shared dpll state */ in intel_atomic_duplicate_dpll_state()
73 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) { in intel_atomic_duplicate_dpll_state()
74 struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i]; in intel_atomic_duplicate_dpll_state()
98 * intel_get_shared_dpll_by_id - get a DPLL given its id
103 * A pointer to the DPLL with @id
109 return &dev_priv->dpll.shared_dplls[id]; in intel_get_shared_dpll_by_id()
113 * intel_get_shared_dpll_id - get the id of a DPLL
115 * @pll: the DPLL
124 long pll_idx = pll - dev_priv->dpll.shared_dplls; in intel_get_shared_dpll_id()
128 pll_idx >= dev_priv->dpll.num_shared_dpll)) in intel_get_shared_dpll_id()
[all …]
/Linux-v5.15/drivers/gpu/drm/gma500/
Dpsb_intel_display.c105 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
152 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
154 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
155 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
157 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
161 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
162 dpll |= in psb_intel_crtc_mode_set()
167 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
170 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
173 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in psb_intel_crtc_mode_set()
[all …]
Doaktrail_crtc.c241 /* Enable the DPLL */ in oaktrail_crtc_dpms()
242 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
244 REG_WRITE_WITH_AUX(map->dpll, temp, i); in oaktrail_crtc_dpms()
245 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
248 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
250 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
253 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
255 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
314 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
316 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
[all …]
Dcdv_intel_display.c206 /* Unlike most Intel display engines, on Cedarview the DPLL registers
208 * DPLL reference clock is on in the DPLL control register, but before
209 * the DPLL is enabled in the DPLL control register.
260 DRM_DEBUG_KMS("use their DPLL for pipe A/B\n"); in cdv_dpll_set_clock_cdv()
583 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
659 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
670 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
672 dpll |= DPLLB_MODE_LVDS; in cdv_intel_crtc_mode_set()
674 dpll |= DPLLB_MODE_DAC_SERIAL; */ in cdv_intel_crtc_mode_set()
675 /* dpll |= (2 << 11); */ in cdv_intel_crtc_mode_set()
[all …]
Dgma_display.c214 /* Enable the DPLL */ in gma_crtc_dpms()
215 temp = REG_READ(map->dpll); in gma_crtc_dpms()
217 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
218 REG_READ(map->dpll); in gma_crtc_dpms()
221 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
222 REG_READ(map->dpll); in gma_crtc_dpms()
225 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
226 REG_READ(map->dpll); in gma_crtc_dpms()
302 /* Disable DPLL */ in gma_crtc_dpms()
303 temp = REG_READ(map->dpll); in gma_crtc_dpms()
[all …]
Doaktrail_hdmi.c282 u32 dspcntr, pipeconf, dpll, temp; in oaktrail_crtc_hdmi_mode_set() local
291 /* Disable dpll if necessary */ in oaktrail_crtc_hdmi_mode_set()
292 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
293 if ((dpll & DPLL_PWRDN) == 0) { in oaktrail_crtc_hdmi_mode_set()
294 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); in oaktrail_crtc_hdmi_mode_set()
303 /* program and enable dpll */ in oaktrail_crtc_hdmi_mode_set()
307 /* Set the DPLL */ in oaktrail_crtc_hdmi_mode_set()
308 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
309 dpll &= ~DPLL_PDIV_MASK; in oaktrail_crtc_hdmi_mode_set()
310 dpll &= ~(DPLL_PWRDN | DPLL_RESET); in oaktrail_crtc_hdmi_mode_set()
[all …]
/Linux-v5.15/include/linux/clk/
Dti.h34 * struct dpll_data - DPLL registers and integration data
35 * @mult_div1_reg: register containing the DPLL M and N bitfields
36 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
37 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
40 * @control_reg: register containing the DPLL mode bitfield
41 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
52 * @max_rate: maximum clock rate for the DPLL
54 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
55 * @idlest_reg: register containing the DPLL idle status bitfield
56 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
[all …]
/Linux-v5.15/arch/arm/mach-omap2/
Dclkt2xxx_dpll.c3 * OMAP2-specific DPLL control functions
21 * _allow_idle - enable DPLL autoidle bits
22 * @clk: struct clk * of the DPLL to operate on
24 * Enable DPLL automatic idle control. The DPLL will enter low-power
26 * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
38 * _deny_idle - prevent DPLL from automatically idling
39 * @clk: struct clk * of the DPLL to operate on
41 * Disable DPLL automatic idle control. No return value.
Dsleep24xx.S35 * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
37 * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
44 * Post sleep we will shift back to using the DPLL. Apparently,
60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
69 /* The DPLL has to be on before we take the DDR out of self refresh */
Dopp2xxx.h14 * respect to each other. These ratio sets are for a given voltage/DPLL
15 * setting. All configurations can be described by a DPLL setting and a ratio
45 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
65 * Voltage/DPLL ratios
218 * describe DPLL combinations to go along with a ratio.
230 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
247 /* #5b (ratio1) target DPLL = 200*2 = 400MHz */
265 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
286 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
305 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
[all …]
Dclkt2xxx_dpllcore.c3 * DPLL + CORE_CLK composite clock functions
15 * XXX The DPLL and CORE clocks should be split into two separate clock
46 * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
80 if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ in omap2_dpllcore_round_rate()
83 } else { /* DPLL clockout x 2 */ in omap2_dpllcore_round_rate()
/Linux-v5.15/Documentation/devicetree/bindings/clock/
Dmicrochip,sparx5-dpll.yaml4 $id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
7 title: Microchip Sparx5 DPLL Clock
13 The Sparx5 DPLL clock controller generates and supplies clock to
18 const: microchip,sparx5-dpll
46 compatible = "microchip,sparx5-dpll";
/Linux-v5.15/drivers/ata/
Dpata_hpt3x2n.c70 /* 66MHz DPLL clocks */
268 * We must use the DPLL for
304 /* See if we should use the DPLL */ in hpt3x2n_use_dpll()
317 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local
324 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer()
333 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local
335 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue()
337 flags |= dpll; in hpt3x2n_qc_issue()
340 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()
377 * hpt3xn_calibrate_dpll - Calibrate the DPLL loop
[all …]
Dpata_hpt37x.c670 * hpt37x_calibrate_dpll - Calibrate the DPLL loop
673 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
694 /* Turn off tuning, we have the DPLL set */ in hpt37x_calibrate_dpll()
979 * use a 50MHz DPLL by choice in hpt37x_init_one()
982 int dpll, adjust; in hpt37x_init_one() local
984 /* Compute DPLL */ in hpt37x_init_one()
985 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; in hpt37x_init_one()
987 f_low = (MHz[clock_slot] * 48) / MHz[dpll]; in hpt37x_init_one()
992 /* Select the DPLL clock. */ in hpt37x_init_one()
1012 pr_err("DPLL did not stabilize!\n"); in hpt37x_init_one()
[all …]
/Linux-v5.15/arch/arm/mach-omap1/
Dsram.S36 strh r0, [r2] @ set dpll into bypass mode
41 strh r0, [r2] @ write new dpll value
49 lock: ldrh r4, [r2], #0 @ read back dpll value
52 tst r4, #1 << 0 @ dpll rate locked?
/Linux-v5.15/drivers/ptp/
Dptp_clockmatrix.c341 u8 dpll = 0; in wait_for_sys_apll_dpll_lock() local
349 err = read_sys_dpll_status(idtcm, &dpll); in wait_for_sys_apll_dpll_lock()
354 dpll &= DPLL_SYS_STATE_MASK; in wait_for_sys_apll_dpll_lock()
357 dpll == DPLL_STATE_LOCKED) { in wait_for_sys_apll_dpll_lock()
359 } else if (dpll == DPLL_STATE_FREERUN || in wait_for_sys_apll_dpll_lock()
360 dpll == DPLL_STATE_HOLDOVER || in wait_for_sys_apll_dpll_lock()
361 dpll == DPLL_STATE_OPEN_LOOP) { in wait_for_sys_apll_dpll_lock()
363 "No wait state: DPLL_SYS_STATE %d", dpll); in wait_for_sys_apll_dpll_lock()
371 "%d ms lock timeout: SYS APLL Loss Lock %d SYS DPLL state %d", in wait_for_sys_apll_dpll_lock()
372 LOCK_TIMEOUT_MS, apll, dpll); in wait_for_sys_apll_dpll_lock()
[all …]
/Linux-v5.15/drivers/tty/serial/
Dip22zilog.h169 #define TRxCDP 3 /* TRxC = DPLL output */
174 #define TCDPLL 0x18 /* Transmit clock = DPLL output */
178 #define RCDPLL 0x60 /* Receive clock = DPLL output */
193 #define DISDPLL 0x60 /* Disable DPLL */
194 #define SSBR 0x80 /* Set DPLL source = BR generator */
195 #define SSRTxC 0xa0 /* Set DPLL source = RTxC */

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