Lines Matching full:dpll
72 /* Copy shared dpll state */ in intel_atomic_duplicate_dpll_state()
73 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) { in intel_atomic_duplicate_dpll_state()
74 struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i]; in intel_atomic_duplicate_dpll_state()
98 * intel_get_shared_dpll_by_id - get a DPLL given its id
103 * A pointer to the DPLL with @id
109 return &dev_priv->dpll.shared_dplls[id]; in intel_get_shared_dpll_by_id()
113 * intel_get_shared_dpll_id - get the id of a DPLL
115 * @pll: the DPLL
124 long pll_idx = pll - dev_priv->dpll.shared_dplls; in intel_get_shared_dpll_id()
128 pll_idx >= dev_priv->dpll.num_shared_dpll)) in intel_get_shared_dpll_id()
143 "asserting DPLL %s with no DPLL\n", onoff(state))) in assert_shared_dpll()
188 * intel_prepare_shared_dpll - call a dpll's prepare hook
189 * @crtc_state: CRTC, and its state, which has a shared dpll
203 mutex_lock(&dev_priv->dpll.lock); in intel_prepare_shared_dpll()
212 mutex_unlock(&dev_priv->dpll.lock); in intel_prepare_shared_dpll()
216 * intel_enable_shared_dpll - enable a CRTC's shared DPLL
217 * @crtc_state: CRTC, and its state, which has a shared DPLL
219 * Enable the shared DPLL used by @crtc.
232 mutex_lock(&dev_priv->dpll.lock); in intel_enable_shared_dpll()
258 mutex_unlock(&dev_priv->dpll.lock); in intel_enable_shared_dpll()
262 * intel_disable_shared_dpll - disable a CRTC's shared DPLL
263 * @crtc_state: CRTC, and its state, which has a shared DPLL
265 * Disable the shared DPLL used by @crtc.
281 mutex_lock(&dev_priv->dpll.lock); in intel_disable_shared_dpll()
304 mutex_unlock(&dev_priv->dpll.lock); in intel_disable_shared_dpll()
323 pll = &dev_priv->dpll.shared_dplls[i]; in intel_find_shared_dpll()
404 * intel_shared_dpll_swap_state - make atomic DPLL configuration effective
407 * This is the dpll version of drm_atomic_helper_swap_state() since the
423 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) { in intel_shared_dpll_swap_state()
425 &dev_priv->dpll.shared_dplls[i]; in intel_shared_dpll_swap_state()
445 hw_state->dpll = val; in ibx_pch_dpll_get_hw_state()
484 intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
491 * DPLL is enabled and the clocks are stable. in ibx_pch_dpll_enable()
495 intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
523 pll = &dev_priv->dpll.shared_dplls[i]; in ibx_get_dpll()
552 "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " in ibx_dump_hw_state()
554 hw_state->dpll, in ibx_dump_hw_state()
568 { "PCH DPLL A", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 },
569 { "PCH DPLL B", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 },
932 refclk = dev_priv->dpll.ref_clks.nssc; in hsw_ddi_wrpll_get_freq()
942 refclk = dev_priv->dpll.ref_clks.ssc; in hsw_ddi_wrpll_get_freq()
1090 i915->dpll.ref_clks.ssc = 135000; in hsw_update_dpll_ref_clks()
1093 i915->dpll.ref_clks.nssc = 24000; in hsw_update_dpll_ref_clks()
1095 i915->dpll.ref_clks.nssc = 135000; in hsw_update_dpll_ref_clks()
1168 /* DPLL 0 */
1170 /* DPLL 0 doesn't support HDMI mode */
1173 /* DPLL 1 */
1179 /* DPLL 2 */
1185 /* DPLL 3 */
1227 drm_err(&dev_priv->drm, "DPLL %d not locked\n", id); in skl_ddi_pll_enable()
1579 * as the DPLL id in this function. in skl_ddi_hdmi_pll_dividers()
1586 i915->dpll.ref_clks.nssc, in skl_ddi_hdmi_pll_dividers()
1613 int ref_clock = i915->dpll.ref_clks.nssc; in skl_ddi_wrpll_get_freq()
1687 * as the DPLL id in this function. in skl_ddi_dp_set_dpll_hw_state()
1775 "Could not set DP dpll HW state.\n"); in skl_get_dpll()
1820 i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref; in skl_update_dpll_ref_clks()
1848 { "DPLL 0", &skl_ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, INTEL_DPLL_ALWAYS_ON },
1849 { "DPLL 1", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
1850 { "DPLL 2", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
1851 { "DPLL 3", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL3, 0 },
2117 struct dpll best_clock; in bxt_ddi_hdmi_pll_dividers()
2255 struct dpll clock; in bxt_ddi_pll_get_freq()
2265 return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock); in bxt_ddi_pll_get_freq()
2303 i915->dpll.ref_clks.ssc = 100000; in bxt_update_dpll_ref_clks()
2304 i915->dpll.ref_clks.nssc = 100000; in bxt_update_dpll_ref_clks()
2446 i915->dpll.ref_clks.nssc == 38400; in ehl_combo_pll_div_frac_wa_needed()
2540 dev_priv->dpll.ref_clks.nssc == 24000 ? in icl_calc_dp_combo_pll()
2563 switch (dev_priv->dpll.ref_clks.nssc) { in icl_calc_tbt_pll()
2565 MISSING_CASE(dev_priv->dpll.ref_clks.nssc); in icl_calc_tbt_pll()
2576 switch (dev_priv->dpll.ref_clks.nssc) { in icl_calc_tbt_pll()
2578 MISSING_CASE(dev_priv->dpll.ref_clks.nssc); in icl_calc_tbt_pll()
2608 int ref_clock = i915->dpll.ref_clks.nssc; in icl_wrpll_ref_clock()
2612 * use 19.2 because the DPLL automatically divides that by 2. in icl_wrpll_ref_clock()
2834 int refclk_khz = dev_priv->dpll.ref_clks.nssc; in icl_calc_mg_pll_state()
3042 ref_clock = dev_priv->dpll.ref_clks.nssc; in icl_ddi_mg_pll_get_freq()
3108 * icl_set_active_port_dpll - select the active port DPLL for a given CRTC
3109 * @crtc_state: state for the CRTC to select the DPLL for
3387 if (dev_priv->dpll.ref_clks.nssc == 38400) { in mg_pll_get_hw_state()
3772 * We need to disable DC states when this DPLL is enabled. in combo_pll_enable()
3905 i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref; in icl_update_dpll_ref_clks()
3953 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
3954 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
3973 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
3974 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
3975 { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
3995 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
3996 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4017 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
4018 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4019 { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
4032 { "DPLL 0", &combo_pll_funcs, DPLL_ID_DG1_DPLL0, 0 },
4033 { "DPLL 1", &combo_pll_funcs, DPLL_ID_DG1_DPLL1, 0 },
4034 { "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 },
4035 { "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 },
4048 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
4049 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4050 { "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 },
4051 { "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 },
4064 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
4065 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4123 dev_priv->dpll.num_shared_dpll = 0; in intel_shared_dpll_init()
4131 dev_priv->dpll.shared_dplls[i].info = &dpll_info[i]; in intel_shared_dpll_init()
4134 dev_priv->dpll.mgr = dpll_mgr; in intel_shared_dpll_init()
4135 dev_priv->dpll.num_shared_dpll = i; in intel_shared_dpll_init()
4136 mutex_init(&dev_priv->dpll.lock); in intel_shared_dpll_init()
4138 BUG_ON(dev_priv->dpll.num_shared_dpll > I915_NUM_PLLS); in intel_shared_dpll_init()
4165 const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr; in intel_reserve_shared_dplls()
4188 const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr; in intel_release_shared_dplls()
4193 * the shared DPLL framework and intel_reserve_shared_dplls() is not in intel_release_shared_dplls()
4203 * intel_update_active_dpll - update the active DPLL for a CRTC/encoder
4205 * @crtc: the CRTC for which to update the active DPLL
4206 * @encoder: encoder determining the type of port DPLL
4208 * Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state,
4210 * DPLL selected will be based on the current mode of the encoder's port.
4217 const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr; in intel_update_active_dpll()
4226 * intel_dpll_get_freq - calculate the DPLL's output frequency
4228 * @pll: DPLL for which to calculate the output frequency
4229 * @pll_state: DPLL state from which to calculate the output frequency
4244 * intel_dpll_get_hw_state - readout the DPLL's hardware state
4246 * @pll: DPLL for which to calculate the output frequency
4247 * @hw_state: DPLL's hardware state
4288 if (i915->dpll.mgr && i915->dpll.mgr->update_ref_clks) in intel_dpll_update_ref_clks()
4289 i915->dpll.mgr->update_ref_clks(i915); in intel_dpll_update_ref_clks()
4296 for (i = 0; i < i915->dpll.num_shared_dpll; i++) in intel_dpll_readout_hw_state()
4297 readout_dpll_hw_state(i915, &i915->dpll.shared_dplls[i]); in intel_dpll_readout_hw_state()
4323 for (i = 0; i < i915->dpll.num_shared_dpll; i++) in intel_dpll_sanitize_state()
4324 sanitize_dpll_state(i915, &i915->dpll.shared_dplls[i]); in intel_dpll_sanitize_state()
4337 if (dev_priv->dpll.mgr) { in intel_dpll_dump_hw_state()
4338 dev_priv->dpll.mgr->dump_hw_state(dev_priv, hw_state); in intel_dpll_dump_hw_state()
4340 /* fallback for platforms that don't use the shared dpll in intel_dpll_dump_hw_state()
4344 "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " in intel_dpll_dump_hw_state()
4346 hw_state->dpll, in intel_dpll_dump_hw_state()