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/Linux-v6.1/drivers/phy/cadence/
Dcdns-dphy.c18 #include <linux/phy/phy-mipi-dphy.h>
24 /* DPHY registers */
95 int (*probe)(struct cdns_dphy *dphy);
96 void (*remove)(struct cdns_dphy *dphy);
97 void (*set_psm_div)(struct cdns_dphy *dphy, u8 div);
98 void (*set_clk_lane_cfg)(struct cdns_dphy *dphy,
100 void (*set_pll_cfg)(struct cdns_dphy *dphy,
102 unsigned long (*get_wakeup_time_ns)(struct cdns_dphy *dphy);
120 static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy, in cdns_dsi_get_dphy_pll_cfg() argument
125 unsigned long pll_ref_hz = clk_get_rate(dphy->pll_ref_clk); in cdns_dsi_get_dphy_pll_cfg()
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Dcdns-dphy-rx.c12 #include <linux/phy/phy-mipi-dphy.h>
71 struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); in cdns_dphy_rx_power_on() local
77 dphy->regs + DPHY_CMN_SSM); in cdns_dphy_rx_power_on()
84 struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); in cdns_dphy_rx_power_off() local
86 writel(0, dphy->regs + DPHY_CMN_SSM); in cdns_dphy_rx_power_off()
118 static int cdns_dphy_rx_wait_lane_ready(struct cdns_dphy_rx *dphy, in cdns_dphy_rx_wait_lane_ready() argument
125 void __iomem *reg = dphy->regs; in cdns_dphy_rx_wait_lane_ready()
148 struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); in cdns_dphy_rx_configure() local
162 writel(reg, dphy->regs + DPHY_BAND_CFG); in cdns_dphy_rx_configure()
165 * Set the required power island phase 2 time. This is mandated by DPHY in cdns_dphy_rx_configure()
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/Linux-v6.1/drivers/phy/allwinner/
Dphy-sun6i-mipi-dphy.c18 #include <linux/phy/phy-mipi-dphy.h>
131 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_init() local
133 reset_control_deassert(dphy->reset); in sun6i_dphy_init()
134 clk_prepare_enable(dphy->mod_clk); in sun6i_dphy_init()
135 clk_set_rate_exclusive(dphy->mod_clk, 150000000); in sun6i_dphy_init()
142 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_configure() local
149 memcpy(&dphy->config, opts, sizeof(dphy->config)); in sun6i_dphy_configure()
154 static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy) in sun6i_dphy_tx_power_on() argument
156 u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0); in sun6i_dphy_tx_power_on()
158 regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG, in sun6i_dphy_tx_power_on()
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/Linux-v6.1/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/
Dsun8i_a83t_dphy.c13 static int sun8i_a83t_dphy_configure(struct phy *dphy, in sun8i_a83t_dphy_configure() argument
19 static int sun8i_a83t_dphy_power_on(struct phy *dphy) in sun8i_a83t_dphy_power_on() argument
21 struct sun8i_a83t_mipi_csi2_device *csi2_dev = phy_get_drvdata(dphy); in sun8i_a83t_dphy_power_on()
36 static int sun8i_a83t_dphy_power_off(struct phy *dphy) in sun8i_a83t_dphy_power_off() argument
38 struct sun8i_a83t_mipi_csi2_device *csi2_dev = phy_get_drvdata(dphy); in sun8i_a83t_dphy_power_off()
57 csi2_dev->dphy = devm_phy_create(dev, NULL, &sun8i_a83t_dphy_ops); in sun8i_a83t_dphy_register()
58 if (IS_ERR(csi2_dev->dphy)) { in sun8i_a83t_dphy_register()
60 return PTR_ERR(csi2_dev->dphy); in sun8i_a83t_dphy_register()
63 phy_set_drvdata(csi2_dev->dphy, csi2_dev); in sun8i_a83t_dphy_register()
/Linux-v6.1/Documentation/devicetree/bindings/phy/
Drockchip-mipi-dphy-rx0.yaml4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
19 const: rockchip,rk3399-mipi-dphy-rx0
29 - const: dphy-ref
30 - const: dphy-cfg
65 mipi_dphy_rx0: mipi-dphy-rx0 {
66 compatible = "rockchip,rk3399-mipi-dphy-rx0";
70 clock-names = "dphy-ref", "dphy-cfg", "grf";
Drockchip,px30-dsi-dphy.yaml4 $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
7 title: Rockchip MIPI DPHY with additional LVDS/TTL modes
18 - rockchip,px30-dsi-dphy
19 - rockchip,rk3128-dsi-dphy
20 - rockchip,rk3368-dsi-dphy
21 - rockchip,rk3568-dsi-dphy
62 compatible = "rockchip,px30-dsi-dphy";
Drockchip-inno-csi-dphy.yaml4 $id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml#
19 - rockchip,px30-csi-dphy
20 - rockchip,rk1808-csi-dphy
21 - rockchip,rk3326-csi-dphy
22 - rockchip,rk3368-csi-dphy
23 - rockchip,rk3568-csi-dphy
71 compatible = "rockchip,px30-csi-dphy";
Dmixel,mipi-dsi-phy.yaml23 - fsl,imx8mq-mipi-dphy
24 - fsl,imx8qxp-mipi-dphy
68 const: fsl,imx8mq-mipi-dphy
82 const: fsl,imx8qxp-mipi-dphy
97 dphy: dphy@30a0030 {
98 compatible = "fsl,imx8mq-mipi-dphy";
Dcdns,dphy.yaml4 $id: http://devicetree.org/schemas/phy/cdns,dphy.yaml#
7 title: Cadence DPHY
15 - cdns,dphy
16 - ti,j721e-dphy
51 compatible = "cdns,dphy";
Dallwinner,sun6i-a31-mipi-dphy.yaml4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml#
19 - const: allwinner,sun6i-a31-mipi-dphy
21 - const: allwinner,sun50i-a64-mipi-dphy
22 - const: allwinner,sun6i-a31-mipi-dphy
65 compatible = "allwinner,sun6i-a31-mipi-dphy";
Dcdns,dphy-rx.yaml4 $id: http://devicetree.org/schemas/phy/cdns,dphy-rx.yaml#
7 title: Cadence DPHY Rx
15 - const: cdns,dphy-rx
38 compatible = "cdns,dphy-rx";
Damlogic,g12a-mipi-dphy-analog.yaml4 $id: "http://devicetree.org/schemas/phy/amlogic,g12a-mipi-dphy-analog.yaml#"
14 const: amlogic,g12a-mipi-dphy-analog
32 compatible = "amlogic,g12a-mipi-dphy-analog";
Damlogic,axg-mipi-dphy.yaml5 $id: "http://devicetree.org/schemas/phy/amlogic,axg-mipi-dphy.yaml#"
16 - amlogic,axg-mipi-dphy
61 compatible = "amlogic,axg-mipi-dphy";
/Linux-v6.1/drivers/media/platform/marvell/
Dmmp-driver.c51 * calc the dphy register values
52 * There are three dphy registers being used.
53 * dphy[0] - CSI2_DPHY3
54 * dphy[1] - CSI2_DPHY5
55 * dphy[2] - CSI2_DPHY6
73 * dphy[0] - CSI2_DPHY3: in mmpcam_calc_dphy()
75 * defines the time that the DPHY in mmpcam_calc_dphy()
99 pdata->dphy[0] = in mmpcam_calc_dphy()
107 pdata->dphy[0] = in mmpcam_calc_dphy()
129 * dphy[2] - CSI2_DPHY6: in mmpcam_calc_dphy()
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/Linux-v6.1/drivers/gpu/drm/kmb/
Dkmb_regs.h647 #define SET_DPHY_INIT_CTRL0(dev, dphy, offset) \ argument
649 ((dphy) + (offset)))
650 #define CLR_DPHY_INIT_CTRL0(dev, dphy, offset) \ argument
652 ((dphy) + (offset)))
659 #define SET_DPHY_FREQ_CTRL0_3(dev, dphy, val) \ argument
661 + (((dphy) / 4) * 4), (dphy % 4) * 8, 6, val)
667 #define GET_STOPSTATE_DATA(dev, dphy) \ argument
669 ((dphy) / 4) * 4)) >> \
670 (((dphy % 4) * 8) + 4)) & 0x03)
675 #define SET_DPHY_TEST_CTRL0(dev, dphy) \ argument
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/Linux-v6.1/drivers/media/platform/rockchip/rkisp1/
Drkisp1-csi.c16 #include <linux/phy/phy-mipi-dphy.h>
174 phy_set_mode(csi->dphy, PHY_MODE_MIPI_DPHY); in rkisp1_csi_start()
175 phy_configure(csi->dphy, &opts); in rkisp1_csi_start()
176 phy_power_on(csi->dphy); in rkisp1_csi_start()
193 phy_power_off(csi->dphy); in rkisp1_csi_stop()
209 * Disable DPHY errctrl interrupt, because this dphy in rkisp1_csi_isr()
222 * Enable DPHY errctrl interrupt again, if mipi have receive in rkisp1_csi_isr()
227 * Enable DPHY errctrl interrupt again, if mipi have receive in rkisp1_csi_isr()
521 csi->dphy = devm_phy_get(rkisp1->dev, "dphy"); in rkisp1_csi_init()
522 if (IS_ERR(csi->dphy)) in rkisp1_csi_init()
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/Linux-v6.1/drivers/phy/amlogic/
DKconfig41 tristate "Meson G12A MIPI Analog DPHY driver"
48 Enable this to support the Meson MIPI Analog DPHY found in Meson G12A
98 tristate "Meson AXG MIPI DPHY driver"
105 Enable this to support the Meson MIPI DPHY found in Meson AXG
/Linux-v6.1/Documentation/devicetree/bindings/soc/rockchip/
Dgrf.yaml146 mipi-dphy-rx0:
149 $ref: "/schemas/phy/rockchip-mipi-dphy-rx0.yaml#"
246 mipi_dphy_rx0: mipi-dphy-rx0 {
247 compatible = "rockchip,rk3399-mipi-dphy-rx0";
251 clock-names = "dphy-ref", "dphy-cfg", "grf";
/Linux-v6.1/drivers/phy/rockchip/
Dphy-rockchip-inno-csidphy.c3 * Rockchip MIPI RX Innosilicon DPHY driver
17 #include <linux/phy/phy-mipi-dphy.h>
252 /* Reset dphy analog part */ in rockchip_inno_csidphy_power_on()
258 /* Reset dphy digital part */ in rockchip_inno_csidphy_power_on()
377 .compatible = "rockchip,px30-csi-dphy",
381 .compatible = "rockchip,rk1808-csi-dphy",
385 .compatible = "rockchip,rk3326-csi-dphy",
389 .compatible = "rockchip,rk3368-csi-dphy",
393 .compatible = "rockchip,rk3568-csi-dphy",
482 MODULE_DESCRIPTION("Rockchip MIPI Innosilicon CSI-DPHY driver");
Dphy-rockchip-dphy-rx0.c3 * Rockchip MIPI Synopsys DPHY RX0 driver
26 #include <linux/phy/phy-mipi-dphy.h>
65 "dphy-ref",
66 "dphy-cfg",
201 /* dphy start */ in rk_dphy_enable()
317 .compatible = "rockchip,rk3399-mipi-dphy-rx0",
376 .name = "rockchip-mipi-dphy-rx0",
383 MODULE_DESCRIPTION("Rockchip MIPI Synopsys DPHY RX0 driver");
/Linux-v6.1/drivers/media/platform/sunxi/sun6i-mipi-csi2/
Dsun6i_mipi_csi2.c179 struct phy *dphy = csi2_dev->dphy; in sun6i_mipi_csi2_s_stream() local
249 ret = phy_reset(dphy); in sun6i_mipi_csi2_s_stream()
255 ret = phy_configure(dphy, &dphy_opts); in sun6i_mipi_csi2_s_stream()
268 ret = phy_power_on(dphy); in sun6i_mipi_csi2_s_stream()
285 phy_power_off(dphy); in sun6i_mipi_csi2_s_stream()
670 csi2_dev->dphy = devm_phy_get(dev, "dphy"); in sun6i_mipi_csi2_resources_setup()
671 if (IS_ERR(csi2_dev->dphy)) { in sun6i_mipi_csi2_resources_setup()
673 ret = PTR_ERR(csi2_dev->dphy); in sun6i_mipi_csi2_resources_setup()
677 ret = phy_init(csi2_dev->dphy); in sun6i_mipi_csi2_resources_setup()
699 phy_exit(csi2_dev->dphy); in sun6i_mipi_csi2_resources_cleanup()
/Linux-v6.1/Documentation/devicetree/bindings/media/
Drockchip-isp1.yaml63 const: dphy
75 description: connection point for sensors at MIPI-DPHY RX0
167 phys = <&dphy>;
168 phy-names = "dphy";
248 phy-names = "dphy";
/Linux-v6.1/drivers/video/fbdev/mmp/hw/
Dmmp_ctrl.h1100 #define DSI_PHY_CTRL_3 0x08C /* DPHY Control Register 3 */
1108 #define DSI_PHY_RCOMP_0 0x0B0 /* DPHY Rcomp Control Register */
1111 #define DSI_PHY_TIME_0 0x0C0 /* DPHY Timing Control Register 0 */
1112 #define DSI_PHY_TIME_1 0x0C4 /* DPHY Timing Control Register 1 */
1113 #define DSI_PHY_TIME_2 0x0C8 /* DPHY Timing Control Register 2 */
1114 #define DSI_PHY_TIME_3 0x0CC /* DPHY Timing Control Register 3 */
1115 #define DSI_PHY_TIME_4 0x0D0 /* DPHY Timing Control Register 4 */
1116 #define DSI_PHY_TIME_5 0x0D4 /* DPHY Timing Control Register 5 */
1208 /* DSI_PHY_CTRL_2 0x0088 DPHY Control Register 2 */
1210 /* DPHY LP Receiver Enable */
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/Linux-v6.1/drivers/staging/media/omap4iss/
Diss_csiphy.c94 reg = phy->dphy.ths_term << REGISTER0_THS_TERM_SHIFT; in csiphy_dphy_config()
95 reg |= phy->dphy.ths_settle << REGISTER0_THS_SETTLE_SHIFT; in csiphy_dphy_config()
100 reg = phy->dphy.tclk_term << REGISTER1_TCLK_TERM_SHIFT; in csiphy_dphy_config()
101 reg |= phy->dphy.tclk_miss << REGISTER1_CTRLCLK_DIV_FACTOR_SHIFT; in csiphy_dphy_config()
102 reg |= phy->dphy.tclk_settle << REGISTER1_TCLK_SETTLE_SHIFT; in csiphy_dphy_config()
211 csi2->phy->dphy = csi2phy; in omap4iss_csiphy_config()
/Linux-v6.1/drivers/phy/freescale/
Dphy-fsl-imx8-mipi-dphy.c35 /* DPHY registers */
91 bool is_combo; /* MIPI DPHY and LVDS PHY combo */
109 /* DPHY PLL parameters */
113 /* DPHY register values */
139 .name = "mipi-dphy",
149 dev_err(&phy->dev, "Failed to write DPHY reg %d: %d\n", reg, in phy_write()
531 dev_err(&phy->dev, "Could not get DPHY lock (%d)!\n", ret); in mixel_dphy_power_on_mipi_dphy()
620 dev_err(&phy->dev, "Failed to set PHY mode to MIPI DPHY\n"); in mixel_dphy_set_mode()
652 { .compatible = "fsl,imx8mq-mipi-dphy",
654 { .compatible = "fsl,imx8qxp-mipi-dphy",
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