Lines Matching full:dphy
1100 #define DSI_PHY_CTRL_3 0x08C /* DPHY Control Register 3 */
1108 #define DSI_PHY_RCOMP_0 0x0B0 /* DPHY Rcomp Control Register */
1111 #define DSI_PHY_TIME_0 0x0C0 /* DPHY Timing Control Register 0 */
1112 #define DSI_PHY_TIME_1 0x0C4 /* DPHY Timing Control Register 1 */
1113 #define DSI_PHY_TIME_2 0x0C8 /* DPHY Timing Control Register 2 */
1114 #define DSI_PHY_TIME_3 0x0CC /* DPHY Timing Control Register 3 */
1115 #define DSI_PHY_TIME_4 0x0D0 /* DPHY Timing Control Register 4 */
1116 #define DSI_PHY_TIME_5 0x0D4 /* DPHY Timing Control Register 5 */
1208 /* DSI_PHY_CTRL_2 0x0088 DPHY Control Register 2 */
1210 /* DPHY LP Receiver Enable */
1213 /* DPHY Data Lane Enable */
1216 /* DPHY Bus Turn Around */
1232 /* DSI_PHY_TIME_0 0x00c0 DPHY Timing Control Register 0 */
1236 /* DPHY HS Trail Period Length */
1239 /* DPHY HS Zero State Length */
1242 /* DPHY HS Prepare State Length */
1246 /* DSI_PHY_TIME_1 0x00c4 DPHY Timing Control Register 1 */
1253 /* DPHY HS Wakeup Period Length */
1257 /* DSI_PHY_TIME_2 0x00c8 DPHY Timing Control Register 2 */
1258 /* DPHY CLK Exit Period Length */
1261 /* DPHY CLK Trail Period Length */
1264 /* DPHY CLK Zero State Length */
1267 /* DPHY CLK LP Length */
1271 /* DSI_PHY_TIME_3 0x00cc DPHY Timing Control Register 3 */
1273 /* DPHY LP Length */
1276 /* DPHY HS req to rdy Length */