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/Linux-v6.1/arch/arm/mm/
Dproc-v7m.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7m.S
8 * This is the "shell" of the ARMv7-M processor support.
14 #include "proc-macros.S"
31 * - loc - location to jump to for soft reset
104 * This should be able to cover all ARMv7-M cores.
140 ldmia sp, {r0-r3, r12}
144 @ Special-purpose control register
150 stmiane sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6
152 teq r8, #0 @ re-evalutae condition
[all …]
Dproc-v7.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7.S
9 #include <linux/arm-smccc.h>
14 #include <asm/asm-offsets.h>
16 #include <asm/pgtable-hwdef.h>
19 #include "proc-macros.S"
22 #include "proc-v7-3level.S"
24 #include "proc-v7-2level.S"
46 * - loc - location to jump to for soft reset
47 * - hyp - indicate if restart occurs in HYP mode
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/arm/
Darm,corstone1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vishnu Banavath <vishnu.banavath@arm.com>
11 - Rui Miguel Silva <rui.silva@linaro.org>
14 ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that
15 provides a flexible compute architecture that combines Cortex‑A and Cortex‑M
18 Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
19 systems for M-Class (or other) processors for adding sensors, connectivity,
25 seamless integration of the optional CryptoCell™-312 cryptographic
[all …]
Dactions.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andreas Färber <afaerber@suse.de>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 # The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC.
19 - items:
20 - enum:
21 - allo,sparky # Allo.com Sparky
22 - cubietech,cubieboard6 # Cubietech CubieBoard6
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/Linux-v6.1/Documentation/devicetree/bindings/arm/stm32/
Dst,mlahb.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: STMicroelectronics STM32 ML-AHB interconnect bindings
10 - Fabien Dessenne <fabien.dessenne@foss.st.com>
11 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
14 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
15 a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory
17 using different buses (see [2]): balancing the Cortex-M firmware accesses
23 - $ref: /schemas/simple-bus.yaml#
[all …]
/Linux-v6.1/Documentation/translations/zh_TW/arm64/
Dsilicon-errata.txt1 SPDX-License-Identifier: GPL-2.0
3 Chinese translated version of Documentation/arm64/silicon-errata.rst
11 M: Will Deacon <will.deacon@arm.com>
15 ---------------------------------------------------------------------
16 Documentation/arm64/silicon-errata.rst 的中文翻譯
30 ---------------------------------------------------------------------
55 相應的內核配置（Kconfig）選項被加在 「內核特性（Kernel Features）」->
66 +----------------+-----------------+-----------------+-------------------------+
67 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
68 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
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/Linux-v6.1/Documentation/translations/zh_CN/arm64/
Dsilicon-errata.txt1 Chinese translated version of Documentation/arm64/silicon-errata.rst
9 M: Will Deacon <will.deacon@arm.com>
12 ---------------------------------------------------------------------
13 Documentation/arm64/silicon-errata.rst 的中文翻译
26 ---------------------------------------------------------------------
51 相应的内核配置（Kconfig）选项被加在 “内核特性（Kernel Features）”->
62 +----------------+-----------------+-----------------+-------------------------+
63 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
64 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
65 | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
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/Linux-v6.1/arch/arm64/boot/dts/sprd/
Dsc9863a.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/clock/sprd,sc9863a-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #address-cells = <2>;
15 #size-cells = <0>;
17 cpu-map {
48 compatible = "arm,cortex-a55";
50 enable-method = "psci";
51 cpu-idle-states = <&CORE_PD>;
56 compatible = "arm,cortex-a55";
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dbcm4708.dtsi5 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
20 stdout-path = "serial0:115200n8";
24 #address-cells = <1>;
25 #size-cells = <0>;
26 enable-method = "brcm,bcm-nsp-smp";
30 compatible = "arm,cortex-a9";
31 next-level-cache = <&L2>;
37 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
39 secondary-boot-reg = <0xffff0400>;
Dvf610m4.dtsi2 * Device tree for VF6xx Cortex-M4 support
6 * This file is dual-licensed: you can use it either under the terms
45 #include "armv7-m.dtsi"
49 #address-cells = <1>;
50 #size-cells = <1>;
56 interrupt-parent = <&nvic>;
/Linux-v6.1/arch/arm64/kernel/
Dcpu_errata.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/arm-smccc.h>
24 if (!is_midr_in_range(midr, &entry->midr_range)) in is_affected_midr_range()
29 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++) in is_affected_midr_range()
30 if (midr == fix->midr_rv && (revidr & fix->revidr_mask)) in is_affected_midr_range()
41 return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list); in is_affected_midr_range_list()
55 return model == entry->midr_range.model; in is_kryo_midr()
102 if (cap->capability == ARM64_WORKAROUND_1542419) in cpu_enable_trap_ctr_access()
135 if (regp->user_mask & ID_AA64ISAR1_EL1_BF16_MASK) in cpu_clear_bf16_from_user_emulation()
136 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; in cpu_clear_bf16_from_user_emulation()
[all …]
/Linux-v6.1/Documentation/arm/stm32/
Doverview.rst6 ------------
8 The STMicroelectronics STM32 family of Cortex-A microprocessors (MPUs) and
9 Cortex-M microcontrollers (MCUs) are supported by the 'STM32' platform of
13 -------------
21 ------
24 contained in arch/arm/mach-stm32
26 There is a generic board board-dt.c in the mach folder which support
32 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
33 - Ludovic Barre <ludovic.barre@st.com>
34 - Gerald Baeza <gerald.baeza@st.com>
/Linux-v6.1/arch/arm/mach-imx/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 Support for Freescale MXC/iMX-based family of processors
92 comment "Cortex-A platforms"
197 comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms"
/Linux-v6.1/arch/arm64/boot/dts/mediatek/
Dmt6795.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/pinctrl/mt6795-pinfunc.h>
13 interrupt-parent = <&sysirq>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 compatible = "arm,psci-0.2";
23 #address-cells = <1>;
24 #size-cells = <0>;
[all …]
Dmt8186.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6 /dts-v1/;
7 #include <dt-bindings/clock/mt8186-clk.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
11 #include <dt-bindings/power/mt8186-power.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/reset/mt8186-resets.h>
[all …]
/Linux-v6.1/arch/arm64/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
234 ARM 64-bit (AArch64) Linux support.
244 depends on $(cc-option,-fpatchable-function-entry=2)
277 # VA_BITS - PAGE_SHIFT - 3
356 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
383 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
388 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
391 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
397 data cache clean-and-invalidate.
405 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
[all …]
/Linux-v6.1/arch/arm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
144 The ARM series is a line of low-power-consumption RISC chip designs
146 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
147 manufactured, but legacy ARM-based PC hardware remains popular in
158 supported in LLD until version 14. The combined range is -/+ 256 MiB,
251 Patch phys-to-virt and virt-to-phys translation functions at
255 This can only be used with non-XIP MMU kernels where the base
302 bool "MMU-based Paged Memory Management Support"
305 Select if you want MMU-based virtualised addressing space
373 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
[all …]
/Linux-v6.1/drivers/gpu/drm/kmb/
DKconfig10 an ARM Cortex A53 CPU with an Intel Movidius VPU.
12 If M is selected the module will be called kmb-drm.
/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dlpc1850-cgu.txt15 - Above text taken from NXP LPC1850 User Manual.
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
22 - compatible:
23 Should be "nxp,lpc1850-cgu"
24 - reg:
27 - #clock-cells:
28 Shall have value <1>. The permitted clock-specifier values
30 - clocks:
34 - clock-indices:
37 - clock-output-names:
[all …]
/Linux-v6.1/arch/arm64/boot/dts/bitmain/
Dbm1880.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/bm1880-clock.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/bitmain,bm1880-reset.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a53";
[all …]
/Linux-v6.1/drivers/firmware/imx/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
18 The System Controller Firmware (SCFW) is a low-level system function
19 which runs on a dedicated Cortex-M core to provide power, clock, and
/Linux-v6.1/Documentation/devicetree/bindings/interrupt-controller/
Darm,nvic.txt4 Cortex-M based processor cores. The NVIC implemented on different SoCs
9 - compatible : should be one of:
10 "arm,v6m-nvic"
11 "arm,v7m-nvic"
12 "arm,v8m-nvic"
13 - interrupt-controller : Identifies the node as an interrupt controller
14 - #interrupt-cells : Specifies the number of cells needed to encode an
21 - reg : Specifies base physical address(s) and size of the NVIC registers.
24 - arm,num-irq-priority-bits: The number of priority bits implemented by the
29 intc: interrupt-controller@e000e100 {
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/sound/
Dfsl,rpmsg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
14 are SAI, DMA controlled by Cortex M core. What we see from Linux
20 - fsl,imx7ulp-rpmsg-audio
21 - fsl,imx8mn-rpmsg-audio
22 - fsl,imx8mm-rpmsg-audio
23 - fsl,imx8mp-rpmsg-audio
24 - fsl,imx8ulp-rpmsg-audio
[all …]
/Linux-v6.1/drivers/soc/ti/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
18 Packets are queued/de-queued by writing/reading descriptor address
40 c-states on AM335x. Also required for rtc and ddr in self-refresh low
44 tristate "TI AMx3 Wkup-M3 IPC Driver"
48 TI AM33XX and AM43XX have a Cortex M3, the Wakeup M3, to handle
61 To compile this as a module, choose M here. The module will be
87 tristate "TI PRU-ICSS Subsystem Platform drivers"
91 TI PRU-ICSS Subsystem platform specific support.
93 Say Y or M here to support the Programmable Realtime Unit (PRU)
/Linux-v6.1/arch/arm/crypto/
Dblake2b-neon-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
29 // M_0-M_3 are occasionally used for other purposes too.
50 // rotation amounts with NEON. (On Cortex-A53 it's the same speed as
51 // vshr.u64 + vsli.u64, while on Cortex-A7 it's faster.)
64 // NEON registers q0-q7. The message block is in q8..q15 (M_0-M_15). The stack
65 // pointer points to a 32-byte aligned buffer containing a copy of q8 and q9
66 // (M_0-M_3), so that they can be reloaded if they are used as temporary
67 // registers. The macro arguments s0-s15 give the order in which the message
76 // a += b + m[blake2b_sigma[r][2*i + 0]];
103 // a += b + m[blake2b_sigma[r][2*i + 1]];
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