Searched +full:cortex +full:- +full:a (Results 1 – 25 of 309) sorted by relevance
12345678910>>...13
| /Linux-v6.1/Documentation/devicetree/bindings/arm/ |
| D | pmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
14 ARM cores often have a PMU for counting cpu and cache events like cache misses
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - apple,firestorm-pmu
[all …]
|
| D | cpus.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 The device tree allows to describe the layout of CPUs in a system through
14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
[all …]
|
| D | arm,corstone1000.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vishnu Banavath <vishnu.banavath@arm.com>
11 - Rui Miguel Silva <rui.silva@linaro.org>
14 ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that
15 provides a flexible compute architecture that combines Cortex‑A and Cortex‑M
18 Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
19 systems for M-Class (or other) processors for adding sensors, connectivity,
21 a secure SoC for a range of rich IoT applications, for example gateways, smart
[all …]
|
| D | arm,scu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
14 with a Snoop Control Unit. The register range is usually 256 (0x100)
18 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
20 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
22 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
28 - arm,cortex-a9-scu
[all …]
|
| D | arm,vexpress-juno.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
11 - Linus Walleij <linus.walleij@linaro.org>
15 multicore Cortex-A class systems. The Versatile Express family contains both
18 The board consist of a motherboard and one or more daughterboards (tiles). The
19 motherboard provides a set of peripherals. Processor and RAM "live" on the
22 The motherboard and each core tile should be described by a separate Device
[all …]
|
| D | arm,realview.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
14 11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to
22 - description: ARM RealView Emulation Baseboard (HBI-0140) was created
23 as a generic platform to test different FPGA designs, and has
26 - const: arm,realview-eb
27 - description: ARM RealView Platform Baseboard for ARM1176JZF-S
28 (HBI-0147) was created as a development board to test ARM TrustZone,
[all …]
|
| D | cpu-capacity.txt | 6 1 - Introduction
15 2 - CPU capacity definition
18 CPU capacity is a number that provides the scheduler information about CPUs
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
25 CPU capacities are obtained by running a suitable benchmark. This binding makes
29 * A "single-threaded" or CPU affine benchmark
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
[all …]
|
| /Linux-v6.1/arch/arm64/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
234 ARM 64-bit (AArch64) Linux support.
244 depends on $(cc-option,-fpatchable-function-entry=2)
277 # VA_BITS - PAGE_SHIFT - 3
356 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
383 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
388 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
391 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
392 and is unable to accept a certain write via this interface, it will
397 data cache clean-and-invalidate.
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/cpu/ |
| D | cpu-topology.txt | 6 1 - Introduction
9 In a SMP system, the hierarchy of CPUs is defined through three entities that
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
35 A topology description containing phandles to cpu nodes that are not compliant
[all …]
|
| D | idle-states.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
21 representing the range of dynamic idle states that a processor can enter at
[all …]
|
| /Linux-v6.1/Documentation/translations/zh_TW/arm64/ |
| D | silicon-errata.txt | 1 SPDX-License-Identifier: GPL-2.0
3 Chinese translated version of Documentation/arm64/silicon-errata.rst
6 original document maintainer directly. However, if you have a problem
9 or if there is a problem with the translation.
15 ---------------------------------------------------------------------
16 Documentation/arm64/silicon-errata.rst 的中文翻譯
30 ---------------------------------------------------------------------
41 A 類：無可行補救措施的嚴重缺陷。
50 情況下，爲將 A 類缺陷當作 C 類處理，可能需要用類似的手段。這些手段被
55 相應的內核配置（Kconfig）選項被加在 「內核特性（Kernel Features）」->
[all …]
|
| /Linux-v6.1/Documentation/translations/zh_CN/arm64/ |
| D | silicon-errata.txt | 1 Chinese translated version of Documentation/arm64/silicon-errata.rst
4 original document maintainer directly. However, if you have a problem
7 or if there is a problem with the translation.
12 ---------------------------------------------------------------------
13 Documentation/arm64/silicon-errata.rst 的中文翻译
26 ---------------------------------------------------------------------
37 A 类：无可行补救措施的严重缺陷。
46 情况下，为将 A 类缺陷当作 C 类处理，可能需要用类似的手段。这些手段被
51 相应的内核配置（Kconfig）选项被加在 “内核特性（Kernel Features）”->
62 +----------------+-----------------+-----------------+-------------------------+
[all …]
|
| /Linux-v6.1/arch/arm/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
144 The ARM series is a line of low-power-consumption RISC chip designs
146 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
147 manufactured, but legacy ARM-based PC hardware remains popular in
148 Europe. There is an ARM Linux project with a web page at
157 relocations, which have been around for a long time, but were not
158 supported in LLD until version 14. The combined range is -/+ 256 MiB,
175 size. This works well for buffers up to a few hundreds kilobytes, but
176 for larger buffers it just a waste of address space. Drivers which has
178 virtual space with just a few allocations.
[all …]
|
| /Linux-v6.1/Documentation/arm64/ |
| D | silicon-errata.rst | 10 so-called "errata", which can cause it to deviate from the architecture
15 Category A A critical error without a viable workaround.
16 Category B A significant or critical error with an acceptable
18 Category C A minor error that is not expected to occur under normal
27 treatment in the operating system. For example, avoiding a particular
28 sequence of code, or configuring the processor in a particular way. A
30 a Category A erratum into a Category C erratum. These are collectively
32 cases (e.g. those cases that both require a non-secure workaround *and*
36 the erratum in question, a Kconfig entry is added under "Kernel
37 Features" -> "ARM errata workarounds via the alternatives framework".
[all …]
|
| /Linux-v6.1/arch/arm/mach-versatile/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
52 bool "Include support for Integrator/IM-PD1"
60 The IM-PD1 is an add-on logic module for the Integrator which
62 The IM-PD1 can be found on the Integrator/PP2 platform.
77 bool "Integrator/CM922T-XA10 core module"
83 bool "Integrator/CM926EJ-S core module"
107 bool "Integrator/CM1026EJ-S core module"
113 bool "Integrator/CM1136JF-S core module"
129 bool "Integrator/CT926 (ARM926EJ-S) core tile"
135 bool "Integrator/CTB36 (ARM1136JF-S) core tile"
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,gic.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
13 ARM SMP cores are often associated with a GIC, providing per processor
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
[all …]
|
| /Linux-v6.1/arch/arm/boot/dts/ |
| D | arm-realview-eb-a9mp.dts | 4 * Permission is hereby granted, free of charge, to any person obtaining a copy
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 /dts-v1/;
24 #include "arm-realview-eb-mp.dtsi"
27 model = "ARM RealView EB Cortex A9 MPCore";
30 * This is the Cortex A9 MPCore tile used with the
34 #address-cells = <1>;
35 #size-cells = <0>;
36 enable-method = "arm,realview-smp";
40 compatible = "arm,cortex-a9";
[all …]
|
| D | arm-realview-pbx-a9.dts | 4 * Permission is hereby granted, free of charge, to any person obtaining a copy
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
28 * This is the RealView Platform Baseboard Explore for Cortex-A9
31 model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
35 #address-cells = <1>;
36 #size-cells = <0>;
37 enable-method = "arm,realview-smp";
39 cpu-map {
[all …]
|
| /Linux-v6.1/arch/arm64/kernel/ |
| D | cpu_errata.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/arm-smccc.h>
24 if (!is_midr_in_range(midr, &entry->midr_range)) in is_affected_midr_range()
29 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++) in is_affected_midr_range()
30 if (midr == fix->midr_rv && (revidr & fix->revidr_mask)) in is_affected_midr_range()
41 return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list); in is_affected_midr_range_list()
55 return model == entry->midr_range.model; in is_kryo_midr()
70 * a consistent CTR_EL0 to make sure that applications behaves in has_mismatched_cache_type()
73 * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 : in has_mismatched_cache_type()
82 * CTR_EL0 matches the system's copy to allow a secondary CPU to boot. in has_mismatched_cache_type()
[all …]
|
| /Linux-v6.1/arch/arm/mm/ |
| D | proc-v7m.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7m.S
8 * This is the "shell" of the ARMv7-M processor support.
14 #include "proc-macros.S"
27 * Perform a soft reset of the system. Put the CPU into the
31 * - loc - location to jump to for soft reset
104 * This should be able to cover all ARMv7-M cores.
140 ldmia sp, {r0-r3, r12}
144 @ Special-purpose control register
150 stmiane sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6
[all …]
|
| D | proc-v7.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7.S
9 #include <linux/arm-smccc.h>
14 #include <asm/asm-offsets.h>
16 #include <asm/pgtable-hwdef.h>
19 #include "proc-macros.S"
22 #include "proc-v7-3level.S"
24 #include "proc-v7-2level.S"
42 * Perform a soft reset of the system. Put the CPU into the
46 * - loc - location to jump to for soft reset
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/watchdog/ |
| D | arm,twd-wdt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/arm,twd-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Timer-Watchdog Watchdog
10 - Rob Herring <robh@kernel.org>
13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
17 The TWD is usually attached to a GIC to deliver its two per-processor
23 - arm,cortex-a9-twd-wdt
[all …]
|
| /Linux-v6.1/drivers/soc/tegra/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
4 # 32-bit ARM SoCs
63 # 64-bit ARM SoCs
75 Tegra124's "4+1" Cortex-A15 CPU complex.
85 the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
86 cores in a switched configuration. It features a GPU of the Maxwell
88 and providing 256 CUDA cores. It supports hardware-accelerated en-
92 Besides the multimedia features it also comes with a variety of I/O
94 name only a few.
104 Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/timer/ |
| D | arm,twd-timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,twd-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Timer-Watchdog Timer
10 - Rob Herring <robh@kernel.org>
13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
17 The TWD is usually attached to a GIC to deliver its two per-processor
23 - arm,cortex-a9-twd-timer
[all …]
|
| D | arm,global_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stuart Menefy <stuart.menefy@st.com>
13 Cortex-A9 are often associated with a per-core Global timer.
18 - enum:
19 - arm,cortex-a5-global-timer
20 - arm,cortex-a9-global-timer
34 - compatible
35 - reg
[all …]
|
12345678910>>...13
