Lines Matching +full:cortex +full:- +full:a
1 # SPDX-License-Identifier: GPL-2.0
144 The ARM series is a line of low-power-consumption RISC chip designs
146 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
147 manufactured, but legacy ARM-based PC hardware remains popular in
148 Europe. There is an ARM Linux project with a web page at
157 relocations, which have been around for a long time, but were not
158 supported in LLD until version 14. The combined range is -/+ 256 MiB,
175 size. This works well for buffers up to a few hundreds kilobytes, but
176 for larger buffers it just a waste of address space. Drivers which has
178 virtual space with just a few allocations.
182 specified order. The order is expressed as a power of two multiplied
251 Patch phys-to-virt and virt-to-phys translation functions at
255 This can only be used with non-XIP MMU kernels where the base
256 of physical memory is at a 2 MiB boundary.
259 this feature (eg, building a kernel for a single machine) and
302 bool "MMU-based Paged Memory Management Support"
305 Select if you want MMU-based virtualised addressing space
327 In general, all Arm machines can be supported in a single
373 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
412 # This is sorted alphabetically by mach-* pathname. However, plat-*
414 # plat- suffix) or along side the corresponding mach-* source.
416 source "arch/arm/mach-actions/Kconfig"
418 source "arch/arm/mach-alpine/Kconfig"
420 source "arch/arm/mach-artpec/Kconfig"
422 source "arch/arm/mach-asm9260/Kconfig"
424 source "arch/arm/mach-aspeed/Kconfig"
426 source "arch/arm/mach-at91/Kconfig"
428 source "arch/arm/mach-axxia/Kconfig"
430 source "arch/arm/mach-bcm/Kconfig"
432 source "arch/arm/mach-berlin/Kconfig"
434 source "arch/arm/mach-clps711x/Kconfig"
436 source "arch/arm/mach-cns3xxx/Kconfig"
438 source "arch/arm/mach-davinci/Kconfig"
440 source "arch/arm/mach-digicolor/Kconfig"
442 source "arch/arm/mach-dove/Kconfig"
444 source "arch/arm/mach-ep93xx/Kconfig"
446 source "arch/arm/mach-exynos/Kconfig"
448 source "arch/arm/mach-footbridge/Kconfig"
450 source "arch/arm/mach-gemini/Kconfig"
452 source "arch/arm/mach-highbank/Kconfig"
454 source "arch/arm/mach-hisi/Kconfig"
456 source "arch/arm/mach-hpe/Kconfig"
458 source "arch/arm/mach-imx/Kconfig"
460 source "arch/arm/mach-iop32x/Kconfig"
462 source "arch/arm/mach-ixp4xx/Kconfig"
464 source "arch/arm/mach-keystone/Kconfig"
466 source "arch/arm/mach-lpc32xx/Kconfig"
468 source "arch/arm/mach-mediatek/Kconfig"
470 source "arch/arm/mach-meson/Kconfig"
472 source "arch/arm/mach-milbeaut/Kconfig"
474 source "arch/arm/mach-mmp/Kconfig"
476 source "arch/arm/mach-moxart/Kconfig"
478 source "arch/arm/mach-mstar/Kconfig"
480 source "arch/arm/mach-mv78xx0/Kconfig"
482 source "arch/arm/mach-mvebu/Kconfig"
484 source "arch/arm/mach-mxs/Kconfig"
486 source "arch/arm/mach-nomadik/Kconfig"
488 source "arch/arm/mach-npcm/Kconfig"
490 source "arch/arm/mach-nspire/Kconfig"
492 source "arch/arm/mach-omap1/Kconfig"
494 source "arch/arm/mach-omap2/Kconfig"
496 source "arch/arm/mach-orion5x/Kconfig"
498 source "arch/arm/mach-oxnas/Kconfig"
500 source "arch/arm/mach-pxa/Kconfig"
502 source "arch/arm/mach-qcom/Kconfig"
504 source "arch/arm/mach-rda/Kconfig"
506 source "arch/arm/mach-realtek/Kconfig"
508 source "arch/arm/mach-rpc/Kconfig"
510 source "arch/arm/mach-rockchip/Kconfig"
512 source "arch/arm/mach-s3c/Kconfig"
514 source "arch/arm/mach-s5pv210/Kconfig"
516 source "arch/arm/mach-sa1100/Kconfig"
518 source "arch/arm/mach-shmobile/Kconfig"
520 source "arch/arm/mach-socfpga/Kconfig"
522 source "arch/arm/mach-spear/Kconfig"
524 source "arch/arm/mach-sti/Kconfig"
526 source "arch/arm/mach-stm32/Kconfig"
528 source "arch/arm/mach-sunplus/Kconfig"
530 source "arch/arm/mach-sunxi/Kconfig"
532 source "arch/arm/mach-tegra/Kconfig"
534 source "arch/arm/mach-uniphier/Kconfig"
536 source "arch/arm/mach-ux500/Kconfig"
538 source "arch/arm/mach-versatile/Kconfig"
540 source "arch/arm/mach-vt8500/Kconfig"
542 source "arch/arm/mach-zynq/Kconfig"
544 # ARMv7-M architecture
553 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
562 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
563 with a range of available cores like Cortex-M3/M4/M7.
593 running on a CPU that supports it.
596 source "arch/arm/Kconfig-nommu"
604 When coming out of either a Wait for Interrupt (WFI) or a Wait for
605 Event (WFE) IDLE states, a specific timing sensitivity exists between
607 instructions. This sensitivity can result in a CPU hang scenario.
609 The software must insert either a Data Synchronization Barrier (DSB)
614 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
617 Executing a SWP instruction to read-only memory does not set bit 11
619 treat the access as a read, preventing a COW from occurring and
635 This option enables the workaround for the 430973 Cortex-A8
636 r1p* erratum. If a code sequence containing an ARM/Thumb
638 same virtual address, whether due to self-modifying code or virtual
639 to physical address re-mapping, Cortex-A8 does not recover from the
640 stale interworking branch prediction. This results in Cortex-A8
645 available in non-secure mode.
648 bool "ARM errata: Processor deadlock when a false hazard is created"
652 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
654 possible for a hazard condition intended for a cache line to instead
655 be incorrectly associated with a different cache line. This false
656 hazard might then cause a processor deadlock. The workaround enables
659 register may not be available in non-secure mode.
666 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
667 erratum. Any asynchronous access to the L2 cache may encounter a
670 workaround disables the write-allocate mode for the L2 cache via the
672 may not be available in non-secure mode.
679 This option enables the workaround for the 742230 Cortex-A9
680 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
682 ordering of the two writes. This workaround sets a specific bit in
683 the diagnostic register of the Cortex-A9 which causes the DMB
684 instruction to behave as a DSB, ensuring the correct behaviour of
692 This option enables the workaround for the 742231 Cortex-A9
694 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
699 register of the Cortex-A9 which reduces the linefill issuing
707 This option enables the workaround for the 643719 Cortex-A9 (prior to
714 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
717 This option enables the workaround for the 720789 Cortex-A9 (prior to
718 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
720 As a consequence of this erratum, some TLB entries which should be
730 This option enables the workaround for the 743622 Cortex-A9
731 (r2p*) erratum. Under very rare conditions, a faulty
732 optimisation in the Cortex-A9 Store Buffer may lead to data
733 corruption. This workaround sets a specific bit in the diagnostic
734 register of the Cortex-A9 which disables the Store Buffer
744 This option enables the workaround for the 751472 Cortex-A9 (prior
746 completion of a following broadcasted operation if the second
747 operation is received by a CPU before the ICIALLUIS has completed,
754 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
755 r3p*) erratum. A speculative memory access may cause a page table walk
757 can populate the micro-TLB with a stale entry which may be hit with
765 This option enables the workaround for the 754327 Cortex-A9 (prior to
767 mechanism and therefore a livelock may occur if an external agent
768 continuously polls a memory location waiting to observe an update.
773 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
778 hit-under-miss enabled). It sets the undocumented bit 31 in
780 register, thus disabling hit-under-miss without putting the
789 affecting Cortex-A9 MPCore with two or more processors (all
790 current revisions). Under certain timing circumstances, a data
794 system. This workaround adds a DSB instruction before the
795 relevant cache maintenance functions and sets a specific bit
802 This option enables the workaround for the 764319 Cortex A-9 erratum.
806 from a privileged mode. This work around catches the exception in a
810 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
813 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
814 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
820 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
823 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
833 This option enables the workaround for the 773022 Cortex-A15
843 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
845 - Cortex-A12 852422: Execution of a sequence of instructions might
846 lead to either a data corruption or a CPU deadlock. Not fixed in
847 any Cortex-A12 cores yet.
849 Feature Register. This bit disables an optimisation applied to a
853 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
856 This option enables the workaround for the 821420 Cortex-A12
857 (all revs) erratum. In very rare timing conditions, a sequence
859 one is in the shadow of a branch or abort, can lead to a
860 deadlock when the VMOV instructions are issued out-of-order.
866 This option enables the workaround for the 825619 Cortex-A12
867 (all revs) erratum. Within rare timing constraints, executing a
868 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
869 and Device/Strongly-Ordered loads and stores might cause deadlock
875 This option enables the workaround for the 857271 Cortex-A12
877 hang. The workaround is expected to have a < 1% performance impact.
883 This option enables the workaround for the 852421 Cortex-A17
885 execution of a DMB ST instruction might fail to properly order
893 - Cortex-A17 852423: Execution of a sequence of instructions might
894 lead to either a data corruption or a CPU deadlock. Not fixed in
895 any Cortex-A17 cores yet.
896 This is identical to Cortex-A12 erratum 852422. It is a separate
904 This option enables the workaround for the 857272 Cortex-A17 erratum.
906 This is identical to Cortex-A12 erratum 857271. It is a separate
920 name of a bus system, i.e. the way the CPU talks to the other stuff
944 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
954 This option should be selected by machines which have an SMP-
957 The only effect of this option is to make the SMP-related
961 bool "Symmetric Multi-Processing"
968 a system with only one CPU, say N. If you have a system with more
971 If you say N here, the kernel will run on uni- and multiprocessor
972 machines, but will use only one CPU of a multiprocessor machine. If
974 uniprocessor machines. On a uniprocessor machine, the kernel
977 See also <file:Documentation/x86/i386/IO-APIC.rst>,
978 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
979 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
988 SMP kernels contain instructions which fail on non-SMP processors.
1015 bool "Multi-core scheduler support"
1018 Multi-core scheduler support improves the CPU scheduler's decision
1019 making when dealing with multi-core CPU chips at a cost of slightly
1027 MultiThreading at a cost of slightly increased overhead in some
1048 bool "Multi-Cluster Power Management"
1052 for (multi-)cluster based systems, such as big.LITTLE based
1078 transparently handle transition between a cluster of A15's
1079 and a cluster of A7's in a big.LITTLE system.
1085 This is a simple and dummy char dev interface to control
1128 int "Maximum number of CPUs (2-32)"
1136 debugging is enabled, which uses half of the per-CPU fixmap
1140 bool "Support for hot-pluggable CPUs"
1153 implementing the PSCI specification for CPU-centric power
1155 0022A ("Power State Coordination Interface System Software on
1159 # a multiplatform kernel, we just want the highest value required by the
1222 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1228 Thumb-2 mode.
1256 ARM ABI (aka EABI). This is only useful if you are using a user
1272 new (ARM EABI) one. It also provides a compatibility layer to
1275 (only for non "thumb" binaries). This option adds a tiny
1276 overhead to all syscalls and produces a slightly larger kernel.
1284 to execute a legacy ABI binary then the result will be
1307 have a large amount of physical memory and/or IO, not all of the
1313 option which should result in a slightly faster kernel.
1318 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1323 For systems with a lot of processes, this can use a lot of
1326 user-space 2nd level page tables to reside in high memory.
1329 bool "Enable use of CPU domains to implement privileged no-access"
1335 use-after-free bugs becoming an exploitable privilege escalation
1339 CPUs with low-vector mappings use a best-efforts implementation.
1362 Disabling this is usually safe for small single-platform
1372 blocks into "zones", where each zone is a power of two number of
1379 a value of 11 means that the largest free memory block is 2^10 pages.
1386 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1387 address divisible by 4. On 32-bit ARM processors, these non-aligned
1389 here, which has a severe performance impact. This is necessary for
1390 correct operation of some network protocols. With an IP-only
1399 cores where a 8-word STM instruction give significantly higher
1400 memory write throughput than a sequence of individual 32bit stores.
1402 A possible side effect is a slight increase in scheduling latency
1406 However, if the CPU data cache is using a write-allocate mode,
1413 under a hypervisor, potentially improving performance significantly
1423 that, there can be a small performance impact.
1443 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1446 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1449 bool "Use a unique stack canary value for each task"
1461 Enable this option to switch to a different method that uses a
1490 by default now. If you are using a board file that is marked
1494 send a reply to the email discussion at
1495 https://lore.kernel.org/all/CAK8P3a0Z9vGEQbVRBo84bSyPFM-LF+hs5w8ZA51g2Z+NsdtDQA@mail.gmail.com/
1510 The physical address at which the ROM-able zImage is to be
1512 ROM-able zImage formats normally set this to a suitable
1522 for the ROM-able zImage which must be available while the
1525 Platforms which normally make use of ROM-able zImage formats
1526 normally set this to a suitable value in their defconfig file.
1542 With this option, the boot code will look for a device tree binary
1546 This is meant as a backward compatibility convenience for those
1547 systems with a bootloader that can't be upgraded to accommodate
1548 the documented boot protocol using a device tree.
1552 look like a DTB header after a reboot if no actual DTB is appended
1553 to zImage. Do not leave this option active in a production kernel
1554 if you don't intend to always append a DTB. Proper passing of the
1555 location into r2 of a bootloader provided DTB is always preferable
1562 Some old bootloaders can't be updated to a DTB capable one, yet
1565 provided by the bootloader and can't always be stored in a static
1566 DTB. To allow a device tree enabled kernel to be used with such
1577 Uses the command-line options passed by the boot loader instead of
1584 The command-line arguments provided by the boot loader will be
1595 architectures, you should supply some command-line options at build
1596 time by entering them here. As a minimum, you should specify the
1606 Uses the command-line options passed by the boot loader. If
1613 The command-line arguments provided by the boot loader will be
1622 command-line options your boot loader passes to the kernel.
1626 bool "Kernel Execute-In-Place from ROM"
1630 Execute-In-Place allows the kernel to run from non-volatile storage
1633 to RAM. Read-write sections, such as the data section and stack,
1664 copied, saving some precious ROM space. A possible drawback is a
1673 kexec is a system call that implements the ability to shutdown your
1674 current kernel, and to start another kernel. It is like a reboot
1675 but it is independent of the system firmware. And like a reboot
1678 It is an ongoing process to be certain the hardware in a machine
1695 loaded in the main kernel with kexec-tools into a specially
1696 reserved region and then later executed after a crash by
1697 kdump/kexec. The crash dump kernel must be compiled to a
1700 For more details see Documentation/admin-guide/kdump/kdump.rst
1708 will be determined at run-time, either by masking the current IP
1726 by UEFI firmware (such as non-volatile variables, realtime
1727 clock, and platform reset). A UEFI stub is also provided to
1741 continue to boot on existing non-UEFI platforms.
1747 to be enabled much earlier than we do on ARM, which is non-trivial.
1770 your machine has an FPA or floating point co-processor podule.
1779 Say Y to include 80-bit support in the kernel floating-point
1780 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1781 Note that gcc does not generate 80-bit operations by default,
1794 It is very simple, and approximately 3-6 times faster than NWFPE.
1798 If you do not feel you need a faster FP emulation you should better
1802 bool "VFP-format floating point maths"
1806 if your hardware includes a VFP unit.
1808 Please see <file:Documentation/arm/vfp/release-notes.rst> for