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/Linux-v5.15/Documentation/gpu/rfc/
Di915_parallel_execbuf.h1 /* SPDX-License-Identifier: MIT */
9 * struct drm_i915_context_engines_parallel_submit - Configure engine for
30 * Returns -EINVAL if hardware context placement configuration is invalid or if
33 * Returns -ENODEV if extension isn't supported on the platform / submission
36 * .. code-block:: none
39 * CS[X] = generic engine of same class, logical instance X
43 * engines=CS[0],CS[1])
46 * CS[0], CS[1]
49 * CS[X] = generic engine of same class, logical instance X
53 * engines=CS[0],CS[2],CS[1],CS[3])
[all …]
/Linux-v5.15/arch/m68k/include/asm/
Dm5307sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5307sim.h -- ColdFire 5307 System Integration Module support.
19 #define CPU_INSTR_PER_JIFFY 3
41 #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
[all …]
Dm5407sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5407sim.h -- ColdFire 5407 System Integration Module support.
19 #define CPU_INSTR_PER_JIFFY 3
41 #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
[all …]
Dm5206sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5206sim.h -- ColdFire 5206 System Integration Module support.
17 #define CPU_INSTR_PER_JIFFY 3
28 #define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */
62 #define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */
63 #define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */
64 #define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
65 #define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */
66 #define MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */
67 #define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */
[all …]
/Linux-v5.15/sound/core/
Dpcm_iec958.c1 // SPDX-License-Identifier: GPL-2.0-only
13 * snd_pcm_create_iec958_consumer_default - create default consumer format IEC958 channel status
14 * @cs: channel status buffer, at least four bytes
17 * Create the consumer format channel status data in @cs of maximum size
18 * @len. When relevant, the configuration-dependant bits will be set as
29 int snd_pcm_create_iec958_consumer_default(u8 *cs, size_t len) in snd_pcm_create_iec958_consumer_default() argument
32 return -EINVAL; in snd_pcm_create_iec958_consumer_default()
34 memset(cs, 0, len); in snd_pcm_create_iec958_consumer_default()
36 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; in snd_pcm_create_iec958_consumer_default()
37 cs[1] = IEC958_AES1_CON_GENERAL; in snd_pcm_create_iec958_consumer_default()
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/Linux-v5.15/drivers/gpu/drm/i915/gt/
Dselftest_engine_pm.c1 // SPDX-License-Identifier: GPL-2.0
23 return *a - *b; in cmp_u64()
29 return (a[1] + 2 * a[2] + a[3]) >> 2; in trifilter()
32 static u32 *emit_wait(u32 *cs, u32 offset, int op, u32 value) in emit_wait() argument
34 *cs++ = MI_SEMAPHORE_WAIT | in emit_wait()
38 *cs++ = value; in emit_wait()
39 *cs++ = offset; in emit_wait()
40 *cs++ = 0; in emit_wait()
42 return cs; in emit_wait()
45 static u32 *emit_store(u32 *cs, u32 offset, u32 value) in emit_store() argument
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Dgen6_engine_cs.c1 // SPDX-License-Identifier: MIT
17 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
21 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
22 * produced by non-pipelined state commands), software needs to first
23 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
26 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
27 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
31 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
32 * BEFORE the pipe-control with a post-sync op and no write-cache
36 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
[all …]
Dselftest_engine_cs.c1 // SPDX-License-Identifier: GPL-2.0
21 return *a - *b; in cmp_u32()
29 atomic_inc(&gt->rps.num_waiters); in perf_begin()
30 schedule_work(&gt->rps.work); in perf_begin()
31 flush_work(&gt->rps.work); in perf_begin()
36 atomic_dec(&gt->rps.num_waiters); in perf_end()
39 return igt_flush_test(gt->i915); in perf_end()
45 rcu_dereference_protected(rq->timeline, in write_timestamp()
48 u32 *cs; in write_timestamp() local
50 cs = intel_ring_begin(rq, 4); in write_timestamp()
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Dgen7_renderclear.c1 // SPDX-License-Identifier: MIT
11 #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS)) argument
47 * a shader on every HW thread, and clear the thread-local registers. in num_primitives()
51 return bv->max_threads; in num_primitives()
58 switch (INTEL_INFO(i915)->gt) { in batch_get_defaults()
61 bv->max_threads = 70; in batch_get_defaults()
64 bv->max_threads = 140; in batch_get_defaults()
66 case 3: in batch_get_defaults()
67 bv->max_threads = 280; in batch_get_defaults()
70 bv->surface_height = 16 * 16; in batch_get_defaults()
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/Linux-v5.15/drivers/s390/char/
Draw3270.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define TUBICMD _IO('3', 3) /* set ccw command for fs reads. */
16 #define TUBOCMD _IO('3', 4) /* set ccw command for fs writes. */
17 #define TUBGETI _IO('3', 7) /* get ccw command for fs reads. */
18 #define TUBGETO _IO('3', 8) /* get ccw command for fs writes. */
19 #define TUBSETMOD _IO('3',12) /* FIXME: what does it do ?*/
20 #define TUBGETMOD _IO('3',13) /* FIXME: what does it do ?*/
44 #define TF_INMDT 0xc1 /* Visible, Set-MDT */
55 /* Extended-Highlighting Bytes */
123 return list_empty(&rq->list); in raw3270_request_final()
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/Linux-v5.15/drivers/memory/
Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
31 #include <linux/omap-gpmc.h>
35 #include <linux/platform_data/mtd-nand-omap2.h>
37 #define DEVICE_NAME "omap-gpmc"
143 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25)
146 #define GPMC_CONFIG1_PAGE_LEN(val) (((val) & 3) << 23)
151 #define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18)
154 #define GPMC_CONFIG1_WAIT_PIN_SEL(val) (((val) & 3) << 16)
[all …]
/Linux-v5.15/Documentation/scsi/
DNinjaSCSI.rst1 .. SPDX-License-Identifier: GPL-2.0
4 WorkBiT NinjaSCSI-3/32Bi driver for Linux
10 This is Workbit corp.'s(http://www.workbit.co.jp/) NinjaSCSI-3
17 :pcmcia-cs: 3.1.27
18 :gcc: gcc-2.95.4
19 :PC card: I-O data PCSC-F (NinjaSCSI-3),
20 I-O data CBSC-II in 16 bit mode (NinjaSCSI-32Bi)
21 :SCSI device: I-O data CDPS-PX24 (CD-ROM drive),
22 Media Intelligent MMO-640GT (Optical disk drive)
24 3. Install
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/Linux-v5.15/drivers/scsi/
Dmyrs.c1 // SPDX-License-Identifier: GPL-2.0
5 * This driver supports the newer, SCSI-based firmware interface only.
10 * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
91 * myrs_reset_cmd - clears critical fields in struct myrs_cmdblk
95 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_reset_cmd()
98 cmd_blk->status = 0; in myrs_reset_cmd()
102 * myrs_qcmd - queues Command for DAC960 V2 Series Controllers.
104 static void myrs_qcmd(struct myrs_hba *cs, struct myrs_cmdblk *cmd_blk) in myrs_qcmd() argument
106 void __iomem *base = cs->io_base; in myrs_qcmd()
107 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_qcmd()
[all …]
/Linux-v5.15/drivers/gpu/drm/i915/selftests/
Di915_perf.c2 * SPDX-License-Identifier: MIT
17 #define TEST_OA_CONFIG_UUID "12345678-1234-1234-1234-1234567890ab"
26 return -ENOMEM; in alloc_empty_config()
28 oa_config->perf = perf; in alloc_empty_config()
29 kref_init(&oa_config->ref); in alloc_empty_config()
31 strlcpy(oa_config->uuid, TEST_OA_CONFIG_UUID, sizeof(oa_config->uuid)); in alloc_empty_config()
33 mutex_lock(&perf->metrics_lock); in alloc_empty_config()
35 oa_config->id = idr_alloc(&perf->metrics_idr, oa_config, 2, 0, GFP_KERNEL); in alloc_empty_config()
36 if (oa_config->id < 0) { in alloc_empty_config()
37 mutex_unlock(&perf->metrics_lock); in alloc_empty_config()
[all …]
/Linux-v5.15/include/linux/mfd/syscon/
Datmel-smc.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
18 #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) argument
19 #define ATMEL_HSMC_SETUP(layout, cs) \ argument
20 ((layout)->timing_regs_offset + ((cs) * 0x14))
21 #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) argument
22 #define ATMEL_HSMC_PULSE(layout, cs) \ argument
23 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
24 #define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8) argument
25 #define ATMEL_HSMC_CYCLE(layout, cs) \ argument
[all …]
/Linux-v5.15/drivers/mfd/
Datmel-smc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
11 #include <linux/mfd/syscon/atmel-smc.h>
15 * atmel_smc_cs_conf_init - initialize a SMC CS conf
16 * @conf: the SMC CS conf to initialize
27 * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
40 * If the @ncycles value is too big to be encoded, -ERANGE is returned and
49 unsigned int lsbmask = GENMASK(msbpos - 1, 0); in atmel_smc_cs_encode_ncycles()
50 unsigned int msbmask = GENMASK(msbwidth - 1, 0); in atmel_smc_cs_encode_ncycles()
65 * We still return -ERANGE in case the caller cares. in atmel_smc_cs_encode_ncycles()
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/memory-controllers/
Dst,stm32-fmc2-ebi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
14 - to translate AXI transactions into the appropriate external device
16 - to meet the access time requirements of the external devices
22 - Christophe Kerello <christophe.kerello@st.com>
26 const: st,stm32mp1-fmc2-ebi
37 "#address-cells":
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/Linux-v5.15/Documentation/devicetree/bindings/gpio/
Dspear_spics.txt1 === ST Microelectronics SPEAr SPI CS Driver ===
17 * compatible: should be defined as "st,spear-spics-gpio"
19 * st-spics,peripcfg-reg: peripheral configuration register offset
20 * st-spics,sw-enable-bit: bit offset to enable sw control
21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high
22 * st-spics,cs-enable-mask: chip select number bit mask
23 * st-spics,cs-enable-shift: chip select number program offset
24 * gpio-controller: Marks the device node as gpio controller
25 * #gpio-cells: should be 1 and will mention chip select number
30 -------
[all …]
/Linux-v5.15/arch/m68k/lib/
Dmemset.c21 char *cs = s; in memset() local
22 *cs++ = c; in memset()
23 s = cs; in memset()
24 count--; in memset()
30 count -= 2; in memset()
36 for (; temp; temp--) in memset()
43 " lsrl #3,%1\n" in memset()
46 "1: movel %3,%0@+\n" in memset()
47 " movel %3,%0@+\n" in memset()
48 " movel %3,%0@+\n" in memset()
[all …]
/Linux-v5.15/drivers/clocksource/
Dem_sti.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Emma Mobile Timer Support - STI
33 struct clocksource cs; member
55 return ioread32(p->base + offs); in em_sti_read()
61 iowrite32(value, p->base + offs); in em_sti_write()
69 ret = clk_enable(p->clk); in em_sti_enable()
71 dev_err(&p->pdev->dev, "cannot enable clock\n"); in em_sti_enable()
80 em_sti_write(p, STI_INTENCLR, 3); in em_sti_enable()
81 em_sti_write(p, STI_INTFFCLR, 3); in em_sti_enable()
92 em_sti_write(p, STI_INTENCLR, 3); in em_sti_disable()
[all …]
Dtimer-microchip-pit64b.c1 // SPDX-License-Identifier: GPL-2.0
3 * 64-bit Periodic Interval Timer driver
25 #define MCHP_PIT64B_MR_SGCLK BIT(3)
51 * struct mchp_pit64b_timer - PIT64B timer data structure
65 * mchp_pit64b_clkevt - PIT64B clockevent data structure
79 * mchp_pit64b_clksrc - PIT64B clocksource data structure
125 writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR); in mchp_pit64b_reset()
126 writel_relaxed(mode | timer->mode, timer->base + MCHP_PIT64B_MR); in mchp_pit64b_reset()
127 writel_relaxed(high, timer->base + MCHP_PIT64B_MSB_PR); in mchp_pit64b_reset()
128 writel_relaxed(low, timer->base + MCHP_PIT64B_LSB_PR); in mchp_pit64b_reset()
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/spi/
Dspi-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
20 pattern: "^spi(@.*|-[0-9a-f])*$"
22 "#address-cells":
25 "#size-cells":
28 cs-gpios:
32 increased automatically with max(cs-gpios, hardware chip selects).
[all …]
Dspi-nxp-fspi.txt4 - compatible : Should be "nxp,lx2160a-fspi"
5 "nxp,imx8qxp-fspi"
6 "nxp,imx8mm-fspi"
7 "nxp,imx8mp-fspi"
8 "nxp,imx8dxl-fspi"
10 - reg : First contains the register location and length,
12 - reg-names : Should contain the resource reg names:
13 - fspi_base: configuration register address space
14 - fspi_mmap: memory mapped address space
15 - interrupts : Should contain the interrupt for the device
[all …]
/Linux-v5.15/arch/mips/bcm63xx/
Ddev-pcmcia.c69 static int __init config_pcmcia_cs(unsigned int cs, in config_pcmcia_cs() argument
74 ret = bcm63xx_set_cs_status(cs, 0); in config_pcmcia_cs()
76 ret = bcm63xx_set_cs_base(cs, base, size); in config_pcmcia_cs()
78 ret = bcm63xx_set_cs_status(cs, 1); in config_pcmcia_cs()
83 unsigned int cs; member
86 } pcmcia_cs[3] __initconst = {
88 .cs = MPI_CS_PCMCIA_COMMON,
93 .cs = MPI_CS_PCMCIA_ATTR,
98 .cs = MPI_CS_PCMCIA_IO,
122 return -ENODEV; in bcm63xx_pcmcia_register()
[all …]
/Linux-v5.15/arch/mips/cavium-octeon/
Docteon-platform.c6 * Copyright (C) 2004-2017 Cavium, Inc.
16 #include <asm/octeon/cvmx-helper-board.h>
22 #include <asm/octeon/cvmx-uctlx-defs.h>
76 if (dev->of_node) { in octeon2_usb_clocks_start()
80 uctl_node = of_get_parent(dev->of_node); in octeon2_usb_clocks_start()
86 "refclk-frequency", &clock_rate); in octeon2_usb_clocks_start()
88 dev_err(dev, "No UCTL \"refclk-frequency\"\n"); in octeon2_usb_clocks_start()
92 "refclk-type", &clock_type); in octeon2_usb_clocks_start()
119 /* Step 3: Configure the reference clock, PHY, and HCLK */ in octeon2_usb_clocks_start()
128 /* 3a */ in octeon2_usb_clocks_start()
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