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/Linux-v5.15/drivers/gpu/drm/i915/gt/
Dgen2_engine_cs.c1 // SPDX-License-Identifier: MIT
17 u32 cmd, *cs; in gen2_emit_flush() local
23 cs = intel_ring_begin(rq, 2 + 4 * num_store_dw); in gen2_emit_flush()
24 if (IS_ERR(cs)) in gen2_emit_flush()
25 return PTR_ERR(cs); in gen2_emit_flush()
27 *cs++ = cmd; in gen2_emit_flush()
28 while (num_store_dw--) { in gen2_emit_flush()
29 *cs++ = MI_STORE_DWORD_INDEX; in gen2_emit_flush()
30 *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32); in gen2_emit_flush()
31 *cs++ = 0; in gen2_emit_flush()
[all …]
Dgen7_renderclear.c1 // SPDX-License-Identifier: MIT
11 #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS)) argument
47 * a shader on every HW thread, and clear the thread-local registers. in num_primitives()
51 return bv->max_threads; in num_primitives()
58 switch (INTEL_INFO(i915)->gt) { in batch_get_defaults()
61 bv->max_threads = 70; in batch_get_defaults()
63 case 2: in batch_get_defaults()
64 bv->max_threads = 140; in batch_get_defaults()
67 bv->max_threads = 280; in batch_get_defaults()
70 bv->surface_height = 16 * 16; in batch_get_defaults()
[all …]
Dintel_migrate.c1 // SPDX-License-Identifier: MIT
31 GEM_BUG_ON(engine->class != COPY_ENGINE_CLASS); in engine_supports_migration()
42 vm->insert_page(vm, px_dma(pt), d->offset, I915_CACHE_NONE, in insert_pte()
43 d->is_lmem ? PTE_LM : 0); in insert_pte()
44 d->offset += PAGE_SIZE; in insert_pte()
57 * to pre-allocate the page directories for the migration VM, this in migrate_vm()
64 * fly. Only 2 implicit vma are used for all migration operations. in migrate_vm()
68 * [0, CHUNK_SZ) -> first object in migrate_vm()
69 * [CHUNK_SZ, 2 * CHUNK_SZ) -> second object in migrate_vm()
70 * [2 * CHUNK_SZ, 2 * CHUNK_SZ + 2 * CHUNK_SZ >> 9] -> PTE in migrate_vm()
[all …]
Dselftest_lrc.c1 // SPDX-License-Identifier: MIT
24 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
26 #define NUM_GPR_DW (NUM_GPR * 2) /* each GPR is 2 dwords */
30 return __vm_create_scratch_for_read_pinned(&gt->ggtt->vm, PAGE_SIZE); in create_scratch()
52 tasklet_hi_schedule(&engine->sched_engine->tasklet); in wait_for_submit()
63 if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) in wait_for_submit()
67 return -ETIME; in wait_for_submit()
76 i915_ggtt_offset(ce->engine->status_page.vma) + in emit_semaphore_signal()
79 u32 *cs; in emit_semaphore_signal() local
85 cs = intel_ring_begin(rq, 4); in emit_semaphore_signal()
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Dselftest_engine_pm.c1 // SPDX-License-Identifier: GPL-2.0
23 return *a - *b; in cmp_u64()
29 return (a[1] + 2 * a[2] + a[3]) >> 2; in trifilter()
32 static u32 *emit_wait(u32 *cs, u32 offset, int op, u32 value) in emit_wait() argument
34 *cs++ = MI_SEMAPHORE_WAIT | in emit_wait()
38 *cs++ = value; in emit_wait()
39 *cs++ = offset; in emit_wait()
40 *cs++ = 0; in emit_wait()
42 return cs; in emit_wait()
45 static u32 *emit_store(u32 *cs, u32 offset, u32 value) in emit_store() argument
[all …]
Dgen6_engine_cs.c1 // SPDX-License-Identifier: MIT
17 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
19 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
21 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
22 * produced by non-pipelined state commands), software needs to first
23 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
26 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
27 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
31 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
32 * BEFORE the pipe-control with a post-sync op and no write-cache
[all …]
Dgen8_engine_cs.c1 // SPDX-License-Identifier: MIT
15 u32 *cs, flags = 0; in gen8_emit_flush_rcs() local
41 if (GRAPHICS_VER(rq->engine->i915) == 9) in gen8_emit_flush_rcs()
45 if (IS_KBL_GT_STEP(rq->engine->i915, 0, STEP_C0)) in gen8_emit_flush_rcs()
57 cs = intel_ring_begin(rq, len); in gen8_emit_flush_rcs()
58 if (IS_ERR(cs)) in gen8_emit_flush_rcs()
59 return PTR_ERR(cs); in gen8_emit_flush_rcs()
62 cs = gen8_emit_pipe_control(cs, 0, 0); in gen8_emit_flush_rcs()
65 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE, in gen8_emit_flush_rcs()
68 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR); in gen8_emit_flush_rcs()
[all …]
Dselftest_engine_cs.c1 // SPDX-License-Identifier: GPL-2.0
21 return *a - *b; in cmp_u32()
29 atomic_inc(&gt->rps.num_waiters); in perf_begin()
30 schedule_work(&gt->rps.work); in perf_begin()
31 flush_work(&gt->rps.work); in perf_begin()
36 atomic_dec(&gt->rps.num_waiters); in perf_end()
39 return igt_flush_test(gt->i915); in perf_end()
45 rcu_dereference_protected(rq->timeline, in write_timestamp()
48 u32 *cs; in write_timestamp() local
50 cs = intel_ring_begin(rq, 4); in write_timestamp()
[all …]
/Linux-v5.15/Documentation/gpu/rfc/
Di915_parallel_execbuf.h1 /* SPDX-License-Identifier: MIT */
6 #define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
9 * struct drm_i915_context_engines_parallel_submit - Configure engine for
30 * Returns -EINVAL if hardware context placement configuration is invalid or if
33 * Returns -ENODEV if extension isn't supported on the platform / submission
36 * .. code-block:: none
39 * CS[X] = generic engine of same class, logical instance X
42 * set_parallel(engine_index=0, width=2, num_siblings=1,
43 * engines=CS[0],CS[1])
46 * CS[0], CS[1]
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/Linux-v5.15/arch/m68k/include/asm/
Dm5307sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5307sim.h -- ColdFire 5307 System Integration Module support.
20 #define MCF_BUSCLK (MCF_CLK / 2)
40 #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
[all …]
Dm5407sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5407sim.h -- ColdFire 5407 System Integration Module support.
20 #define MCF_BUSCLK (MCF_CLK / 2)
40 #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
[all …]
Dm5206sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5206sim.h -- ColdFire 5206 System Integration Module support.
27 #define MCFSIM_ICR2 (MCF_MBAR + 0x15) /* Intr Ctrl reg 2 */
62 #define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */
63 #define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */
64 #define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
65 #define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */
66 #define MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */
67 #define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */
68 #define MCFSIM_CSAR2 (MCF_MBAR + 0x7c) /* CS 2 Address reg */
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/memory-controllers/
Dti-aemif.txt4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
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Dst,stm32-fmc2-ebi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics Flexible Memory Controller 2 (FMC2) Bindings
11 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
14 - to translate AXI transactions into the appropriate external device
16 - to meet the access time requirements of the external devices
22 - Christophe Kerello <christophe.kerello@st.com>
26 const: st,stm32mp1-fmc2-ebi
[all …]
Domap-gpmc.txt7 - compatible: Should be set to one of the following:
9 ti,omap2420-gpmc (omap2420)
10 ti,omap2430-gpmc (omap2430)
11 ti,omap3430-gpmc (omap3430 & omap3630)
12 ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
13 ti,am3352-gpmc (am335x devices)
15 - reg: A resource specifier for the register space
17 - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
19 - #address-cells: Must be set to 2 to allow memory address translation
20 - #size-cells: Must be set to 1 to allow CS address passing
[all …]
/Linux-v5.15/drivers/gpu/drm/i915/gvt/
Dmmio_context.c2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
53 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
85 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
152 u32 l3cc_table[GEN9_MOCS_SIZE / 2];
165 struct intel_gvt *gvt = engine->i915->gvt; in load_render_mocs()
166 struct intel_uncore *uncore = engine->uncore; in load_render_mocs()
167 u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt; in load_render_mocs()
168 u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list; in load_render_mocs()
177 if (!HAS_ENGINE(engine->gt, ring_id)) in load_render_mocs()
189 for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) { in load_render_mocs()
[all …]
/Linux-v5.15/include/linux/mfd/syscon/
Datmel-smc.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
18 #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) argument
19 #define ATMEL_HSMC_SETUP(layout, cs) \ argument
20 ((layout)->timing_regs_offset + ((cs) * 0x14))
21 #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) argument
22 #define ATMEL_HSMC_PULSE(layout, cs) \ argument
23 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
24 #define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8) argument
25 #define ATMEL_HSMC_CYCLE(layout, cs) \ argument
[all …]
/Linux-v5.15/drivers/memory/
Dstm32-fmc2-ebi.c1 // SPDX-License-Identifier: GPL-2.0
31 #define FMC2_BCR_MTYP GENMASK(3, 2)
146 * struct stm32_fmc2_prop - STM32 FMC2 EBI property
170 const struct stm32_fmc2_prop *prop, int cs);
171 u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
174 int cs, u32 setup);
179 int cs) in stm32_fmc2_ebi_check_mux() argument
183 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_mux()
188 return -EINVAL; in stm32_fmc2_ebi_check_mux()
193 int cs) in stm32_fmc2_ebi_check_waitcfg() argument
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/spi/
Dspi-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
20 pattern: "^spi(@.*|-[0-9a-f])*$"
22 "#address-cells":
25 "#size-cells":
28 cs-gpios:
32 increased automatically with max(cs-gpios, hardware chip selects).
[all …]
/Linux-v5.15/drivers/scsi/
Dmyrs.c1 // SPDX-License-Identifier: GPL-2.0
5 * This driver supports the newer, SCSI-based firmware interface only.
10 * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
91 * myrs_reset_cmd - clears critical fields in struct myrs_cmdblk
95 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_reset_cmd()
98 cmd_blk->status = 0; in myrs_reset_cmd()
102 * myrs_qcmd - queues Command for DAC960 V2 Series Controllers.
104 static void myrs_qcmd(struct myrs_hba *cs, struct myrs_cmdblk *cmd_blk) in myrs_qcmd() argument
106 void __iomem *base = cs->io_base; in myrs_qcmd()
107 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_qcmd()
[all …]
/Linux-v5.15/drivers/gpu/drm/i915/selftests/
Di915_perf.c2 * SPDX-License-Identifier: MIT
17 #define TEST_OA_CONFIG_UUID "12345678-1234-1234-1234-1234567890ab"
26 return -ENOMEM; in alloc_empty_config()
28 oa_config->perf = perf; in alloc_empty_config()
29 kref_init(&oa_config->ref); in alloc_empty_config()
31 strlcpy(oa_config->uuid, TEST_OA_CONFIG_UUID, sizeof(oa_config->uuid)); in alloc_empty_config()
33 mutex_lock(&perf->metrics_lock); in alloc_empty_config()
35 oa_config->id = idr_alloc(&perf->metrics_idr, oa_config, 2, 0, GFP_KERNEL); in alloc_empty_config()
36 if (oa_config->id < 0) { in alloc_empty_config()
37 mutex_unlock(&perf->metrics_lock); in alloc_empty_config()
[all …]
/Linux-v5.15/include/linux/
Dclocksource.h1 /* SPDX-License-Identifier: GPL-2.0 */
35 * struct clocksource - hardware abstraction for a free running counter
36 * Provides mostly state-free accessors to the underlying hardware.
48 * @archdata: Optional arch-specific data
57 * 1-99: Unfit for real use
59 * 100-199: Base level usability.
61 * 200-299: Good.
63 * 300-399: Desired.
65 * 400-499: Perfect
66 * The ideal clocksource. A must-use where
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/Linux-v5.15/arch/mips/include/asm/netlogic/xlr/
Dflash.h2 * Copyright (c) 2003-2012 Broadcom Corporation
7 * General Public License (GPL) Version 2, available from the file
17 * 2. Redistributions in binary form must reproduce the above copyright
37 #define FLASH_CSBASE_ADDR(cs) (cs) argument
38 #define FLASH_CSADDR_MASK(cs) (0x10 + (cs)) argument
39 #define FLASH_CSDEV_PARM(cs) (0x20 + (cs)) argument
40 #define FLASH_CSTIME_PARMA(cs) (0x30 + (cs)) argument
41 #define FLASH_CSTIME_PARMB(cs) (0x40 + (cs)) argument
48 #define FLASH_NAND_CLE(cs) (0x90 + (cs)) argument
49 #define FLASH_NAND_ALE(cs) (0xa0 + (cs)) argument
/Linux-v5.15/drivers/spi/
Dspi-omap2-mcspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/dma-mapping.h>
30 #include <linux/platform_data/spi-omap2-mcspi.h>
47 /* per-channel banks, 0x14 bytes each, first is: */
54 /* per-register bitmasks: */
58 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
63 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
82 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
90 /* We have 2 DMA channels per CS, one for RX and one for TX */
115 struct list_head cs; member
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/Linux-v5.15/Documentation/devicetree/bindings/bus/
Dimx-weim.txt5 wireless and mobile applications that use low-power technology.
11 - compatible: Should contain one of the following:
12 "fsl,imx1-weim"
13 "fsl,imx27-weim"
14 "fsl,imx51-weim"
15 "fsl,imx50-weim"
16 "fsl,imx6q-weim"
17 - reg: A resource specifier for the register space
19 - clocks: the clock, see the example below.
20 - #address-cells: Must be set to 2 to allow memory address translation
[all …]

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