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/Linux-v5.15/drivers/gpu/drm/i915/gt/
Dgen8_engine_cs.c1 // SPDX-License-Identifier: MIT
15 u32 *cs, flags = 0; in gen8_emit_flush_rcs() local
41 if (GRAPHICS_VER(rq->engine->i915) == 9) in gen8_emit_flush_rcs()
45 if (IS_KBL_GT_STEP(rq->engine->i915, 0, STEP_C0)) in gen8_emit_flush_rcs()
57 cs = intel_ring_begin(rq, len); in gen8_emit_flush_rcs()
58 if (IS_ERR(cs)) in gen8_emit_flush_rcs()
59 return PTR_ERR(cs); in gen8_emit_flush_rcs()
62 cs = gen8_emit_pipe_control(cs, 0, 0); in gen8_emit_flush_rcs()
65 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE, in gen8_emit_flush_rcs()
66 0); in gen8_emit_flush_rcs()
[all …]
Dgen6_engine_cs.c1 // SPDX-License-Identifier: MIT
17 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
21 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
22 * produced by non-pipelined state commands), software needs to first
23 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
24 * 0.
26 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
27 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
31 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
32 * BEFORE the pipe-control with a post-sync op and no write-cache
[all …]
Dgen7_renderclear.c1 // SPDX-License-Identifier: MIT
10 #define GT3_INLINE_DATA_DELAYS 0x1E00
11 #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS)) argument
47 * a shader on every HW thread, and clear the thread-local registers. in num_primitives()
51 return bv->max_threads; in num_primitives()
58 switch (INTEL_INFO(i915)->gt) { in batch_get_defaults()
61 bv->max_threads = 70; in batch_get_defaults()
64 bv->max_threads = 140; in batch_get_defaults()
67 bv->max_threads = 280; in batch_get_defaults()
70 bv->surface_height = 16 * 16; in batch_get_defaults()
[all …]
Dgen2_engine_cs.c1 // SPDX-License-Identifier: MIT
17 u32 cmd, *cs; in gen2_emit_flush() local
23 cs = intel_ring_begin(rq, 2 + 4 * num_store_dw); in gen2_emit_flush()
24 if (IS_ERR(cs)) in gen2_emit_flush()
25 return PTR_ERR(cs); in gen2_emit_flush()
27 *cs++ = cmd; in gen2_emit_flush()
28 while (num_store_dw--) { in gen2_emit_flush()
29 *cs++ = MI_STORE_DWORD_INDEX; in gen2_emit_flush()
30 *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32); in gen2_emit_flush()
31 *cs++ = 0; in gen2_emit_flush()
[all …]
Dintel_migrate.c1 // SPDX-License-Identifier: MIT
31 GEM_BUG_ON(engine->class != COPY_ENGINE_CLASS); in engine_supports_migration()
42 vm->insert_page(vm, px_dma(pt), d->offset, I915_CACHE_NONE, in insert_pte()
43 d->is_lmem ? PTE_LM : 0); in insert_pte()
44 d->offset += PAGE_SIZE; in insert_pte()
57 * to pre-allocate the page directories for the migration VM, this in migrate_vm()
68 * [0, CHUNK_SZ) -> first object in migrate_vm()
69 * [CHUNK_SZ, 2 * CHUNK_SZ) -> second object in migrate_vm()
70 * [2 * CHUNK_SZ, 2 * CHUNK_SZ + 2 * CHUNK_SZ >> 9] -> PTE in migrate_vm()
75 * i.e. within the same non-preemptible window so that we do not switch in migrate_vm()
[all …]
Dselftest_lrc.c1 // SPDX-License-Identifier: MIT
24 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
30 return __vm_create_scratch_for_read_pinned(&gt->ggtt->vm, PAGE_SIZE); in create_scratch()
52 tasklet_hi_schedule(&engine->sched_engine->tasklet); in wait_for_submit()
59 return 0; in wait_for_submit()
63 if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) in wait_for_submit()
64 return 0; in wait_for_submit()
67 return -ETIME; in wait_for_submit()
76 i915_ggtt_offset(ce->engine->status_page.vma) + in emit_semaphore_signal()
79 u32 *cs; in emit_semaphore_signal() local
[all …]
Dselftest_engine_pm.c1 // SPDX-License-Identifier: GPL-2.0
23 return *a - *b; in cmp_u64()
32 static u32 *emit_wait(u32 *cs, u32 offset, int op, u32 value) in emit_wait() argument
34 *cs++ = MI_SEMAPHORE_WAIT | in emit_wait()
38 *cs++ = value; in emit_wait()
39 *cs++ = offset; in emit_wait()
40 *cs++ = 0; in emit_wait()
42 return cs; in emit_wait()
45 static u32 *emit_store(u32 *cs, u32 offset, u32 value) in emit_store() argument
47 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; in emit_store()
[all …]
Dgen8_engine_cs.h1 /* SPDX-License-Identifier: MIT */
34 u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
35 u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
37 u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
38 u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
39 u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
44 memset(batch, 0, 6 * sizeof(u32)); in __gen8_emit_pipe_control()
46 batch[0] = GFX_OP_PIPE_CONTROL(6) | flags0; in __gen8_emit_pipe_control()
55 return __gen8_emit_pipe_control(batch, 0, flags, offset); in gen8_emit_pipe_control()
64 __gen8_emit_write_rcs(u32 *cs, u32 value, u32 offset, u32 flags0, u32 flags1) in __gen8_emit_write_rcs() argument
[all …]
/Linux-v5.15/drivers/scsi/
Dmyrs.c1 // SPDX-License-Identifier: GPL-2.0
5 * This driver supports the newer, SCSI-based firmware interface only.
10 * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
52 for (i = 0; i < ARRAY_SIZE(myrs_devstate_name_list); i++) { in myrs_devstate_name()
83 for (i = 0; i < ARRAY_SIZE(myrs_raid_level_name_list); i++) { in myrs_raid_level_name()
91 * myrs_reset_cmd - clears critical fields in struct myrs_cmdblk
95 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_reset_cmd()
97 memset(mbox, 0, sizeof(union myrs_cmd_mbox)); in myrs_reset_cmd()
98 cmd_blk->status = 0; in myrs_reset_cmd()
102 * myrs_qcmd - queues Command for DAC960 V2 Series Controllers.
[all …]
/Linux-v5.15/kernel/time/
Dclocksource.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include "tick-internal.h"
24 * clocks_calc_mult_shift - calculate mult/shift factors for scaled math of clocks
59 sftacc--; in clocks_calc_mult_shift()
66 for (sft = 32; sft > 0; sft--) { in clocks_calc_mult_shift()
70 if ((tmp >> sftacc) == 0) in clocks_calc_mult_shift()
78 /*[Clocksource internal variables]---------
88 * Name of the user-specified clocksource.
100 * Also a default for cs->uncertainty_margin when registering clocks.
108 * a lower bound for cs->uncertainty_margin values when registering clocks.
[all …]
/Linux-v5.15/drivers/misc/habanalabs/common/
Dcommand_submission.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
18 * enum hl_cs_wait_status - cs wait status
19 * @CS_WAIT_STATUS_BUSY: cs was not completed yet
20 * @CS_WAIT_STATUS_COMPLETED: cs completed
21 * @CS_WAIT_STATUS_GONE: cs completed but fence is already gone
39 struct hl_device *hdev = hw_sob->hdev; in hl_sob_reset()
41 dev_dbg(hdev->dev, "reset sob id %u\n", hw_sob->sob_id); in hl_sob_reset()
43 hdev->asic_funcs->reset_sob(hdev, hw_sob); in hl_sob_reset()
45 hw_sob->need_reset = false; in hl_sob_reset()
[all …]
Dhw_queue.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
13 * hl_queue_add_ptr - add to pi or ci and checks if it wraps around
23 ptr &= ((HL_QUEUE_LENGTH << 1) - 1); in hl_hw_queue_add_ptr()
28 return atomic_read(ci) & ((queue_len << 1) - 1); in queue_ci_get()
33 int delta = (q->pi - queue_ci_get(&q->ci, queue_len)); in queue_free_slots()
35 if (delta >= 0) in queue_free_slots()
36 return (queue_len - delta); in queue_free_slots()
38 return (abs(delta) - queue_len); in queue_free_slots()
41 void hl_hw_queue_update_ci(struct hl_cs *cs) in hl_hw_queue_update_ci() argument
[all …]
/Linux-v5.15/drivers/memory/
Dstm32-fmc2-ebi.c1 // SPDX-License-Identifier: GPL-2.0
16 #define FMC2_BCR1 0x0
17 #define FMC2_BTR1 0x4
18 #define FMC2_BCR(x) ((x) * 0x8 + FMC2_BCR1)
19 #define FMC2_BTR(x) ((x) * 0x8 + FMC2_BTR1)
20 #define FMC2_PCSCNTR 0x20
21 #define FMC2_BWTR1 0x104
22 #define FMC2_BWTR(x) ((x) * 0x8 + FMC2_BWTR1)
29 #define FMC2_BCR_MBKEN BIT(0)
46 #define FMC2_BXTR_ADDSET GENMASK(3, 0)
[all …]
Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
31 #include <linux/omap-gpmc.h>
35 #include <linux/platform_data/mtd-nand-omap2.h>
37 #define DEVICE_NAME "omap-gpmc"
40 #define GPMC_REVISION 0x00
41 #define GPMC_SYSCONFIG 0x10
42 #define GPMC_SYSSTATUS 0x14
43 #define GPMC_IRQSTATUS 0x18
[all …]
/Linux-v5.15/Documentation/gpu/rfc/
Di915_parallel_execbuf.h1 /* SPDX-License-Identifier: MIT */
9 * struct drm_i915_context_engines_parallel_submit - Configure engine for
30 * Returns -EINVAL if hardware context placement configuration is invalid or if
33 * Returns -ENODEV if extension isn't supported on the platform / submission
36 * .. code-block:: none
39 * CS[X] = generic engine of same class, logical instance X
42 * set_parallel(engine_index=0, width=2, num_siblings=1,
43 * engines=CS[0],CS[1])
46 * CS[0], CS[1]
49 * CS[X] = generic engine of same class, logical instance X
[all …]
/Linux-v5.15/drivers/mfd/
Datmel-smc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
11 #include <linux/mfd/syscon/atmel-smc.h>
15 * atmel_smc_cs_conf_init - initialize a SMC CS conf
16 * @conf: the SMC CS conf to initialize
18 * Set all fields to 0 so that one can start defining a new config.
22 memset(conf, 0, sizeof(*conf)); in atmel_smc_cs_conf_init()
27 * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
40 * If the @ncycles value is too big to be encoded, -ERANGE is returned and
41 * the encodedval is contains the maximum val. Otherwise, 0 is returned.
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/memory-controllers/
Dti-aemif.txt4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
[all …]
Dst,stm32-fmc2-ebi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
14 - to translate AXI transactions into the appropriate external device
16 - to meet the access time requirements of the external devices
22 - Christophe Kerello <christophe.kerello@st.com>
26 const: st,stm32mp1-fmc2-ebi
37 "#address-cells":
[all …]
/Linux-v5.15/arch/m68k/include/asm/
Dm5307sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5307sim.h -- ColdFire 5307 System Integration Module support.
27 #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status reg */
28 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
29 #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
30 #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
31 #define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
32 #define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Itr Assignment */
33 #define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl Reg */
34 #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
[all …]
/Linux-v5.15/include/linux/mfd/syscon/
Datmel-smc.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
18 #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) argument
19 #define ATMEL_HSMC_SETUP(layout, cs) \ argument
20 ((layout)->timing_regs_offset + ((cs) * 0x14))
21 #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) argument
22 #define ATMEL_HSMC_PULSE(layout, cs) \ argument
23 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
24 #define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8) argument
25 #define ATMEL_HSMC_CYCLE(layout, cs) \ argument
[all …]
/Linux-v5.15/kernel/cgroup/
Dcpuset.c7 * Copyright (C) 2004-2007 Silicon Graphics, Inc.
11 * sysfs is Copyright (c) 2001-3 Patrick Mochel
13 * 2003-10-10 Written by Simon Derr.
14 * 2003-10-22 Updates by Stephen Hemminger.
15 * 2004 May-July Rework by Paul Jackson.
59 #include <linux/backing-dev.h>
89 * The user-configured masks can only be changed by writing to
103 * The user-configured masks are always the same with effective masks.
106 /* user-configured CPUs and Memory Nodes allow to tasks */
115 * CPUs allocated to child sub-partitions (default hierarchy only)
[all …]
/Linux-v5.15/fs/fuse/
Ddev.c3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
29 #define FUSE_INT_REQ_BIT (1ULL << 0)
37 * Lockless access is OK, because file->private data is set in fuse_get_dev()
40 return READ_ONCE(file->private_data); in fuse_get_dev()
45 INIT_LIST_HEAD(&req->list); in fuse_request_init()
46 INIT_LIST_HEAD(&req->intr_entry); in fuse_request_init()
47 init_waitqueue_head(&req->waitq); in fuse_request_init()
48 refcount_set(&req->count, 1); in fuse_request_init()
49 __set_bit(FR_PENDING, &req->flags); in fuse_request_init()
50 req->fm = fm; in fuse_request_init()
[all …]
/Linux-v5.15/sound/core/
Dpcm_iec958.c1 // SPDX-License-Identifier: GPL-2.0-only
13 * snd_pcm_create_iec958_consumer_default - create default consumer format IEC958 channel status
14 * @cs: channel status buffer, at least four bytes
17 * Create the consumer format channel status data in @cs of maximum size
18 * @len. When relevant, the configuration-dependant bits will be set as
29 int snd_pcm_create_iec958_consumer_default(u8 *cs, size_t len) in snd_pcm_create_iec958_consumer_default() argument
32 return -EINVAL; in snd_pcm_create_iec958_consumer_default()
34 memset(cs, 0, len); in snd_pcm_create_iec958_consumer_default()
36 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; in snd_pcm_create_iec958_consumer_default()
37 cs[1] = IEC958_AES1_CON_GENERAL; in snd_pcm_create_iec958_consumer_default()
[all …]
/Linux-v5.15/arch/mips/bcm63xx/
Dcs.c24 static int is_valid_cs(unsigned int cs) in is_valid_cs() argument
26 if (cs > 6) in is_valid_cs()
27 return 0; in is_valid_cs()
35 int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size) in bcm63xx_set_cs_base() argument
40 if (!is_valid_cs(cs)) in bcm63xx_set_cs_base()
41 return -EINVAL; in bcm63xx_set_cs_base()
45 return -EINVAL; in bcm63xx_set_cs_base()
48 return -EINVAL; in bcm63xx_set_cs_base()
51 /* 8k => 0 - 256M => 15 */ in bcm63xx_set_cs_base()
52 val |= (ilog2(size) - ilog2(8 * 1024)) << MPI_CSBASE_SIZE_SHIFT; in bcm63xx_set_cs_base()
[all …]
/Linux-v5.15/net/ceph/
Dstring_table.c1 // SPDX-License-Identifier: GPL-2.0
13 struct ceph_string *cs, *exist; in ceph_find_or_create_string() local
23 if (ret > 0) in ceph_find_or_create_string()
24 p = &(*p)->rb_left; in ceph_find_or_create_string()
25 else if (ret < 0) in ceph_find_or_create_string()
26 p = &(*p)->rb_right; in ceph_find_or_create_string()
31 if (exist && !kref_get_unless_zero(&exist->kref)) { in ceph_find_or_create_string()
32 rb_erase(&exist->node, &string_tree); in ceph_find_or_create_string()
33 RB_CLEAR_NODE(&exist->node); in ceph_find_or_create_string()
40 cs = kmalloc(sizeof(*cs) + len + 1, GFP_NOFS); in ceph_find_or_create_string()
[all …]

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