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/Linux-v5.15/drivers/net/ethernet/intel/e1000e/
Dregs.h32 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
121 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
122 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
123 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
124 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
125 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
126 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
127 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
128 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
129 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
[all …]
/Linux-v5.15/drivers/net/ethernet/intel/igc/
Digc_regs.h135 #define IGC_CRCERRS 0x04000 /* CRC Error Count - R/clr */
136 #define IGC_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
137 #define IGC_RXERRC 0x0400C /* Receive Error Count - R/clr */
138 #define IGC_MPC 0x04010 /* Missed Packet Count - R/clr */
139 #define IGC_SCC 0x04014 /* Single Collision Count - R/clr */
140 #define IGC_ECOL 0x04018 /* Excessive Collision Count - R/clr */
141 #define IGC_MCC 0x0401C /* Multiple Collision Count - R/clr */
142 #define IGC_LATECOL 0x04020 /* Late Collision Count - R/clr */
143 #define IGC_COLC 0x04028 /* Collision Count - R/clr */
144 #define IGC_RERC 0x0402C /* Receive Error Count - R/clr */
[all …]
/Linux-v5.15/drivers/net/ethernet/intel/igb/
De1000_regs.h21 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
30 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
188 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
189 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
190 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
191 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
192 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
193 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
194 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
195 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
[all …]
/Linux-v5.15/arch/arm/mach-rpc/
Dirq.c14 #define CLR 0x04 macro
39 writeb(mask, base + CLR); in iomd_irq_mask_ack()
75 unsigned int irq, clr, set; in rpc_init_irq() local
86 clr = IRQ_NOREQUEST; in rpc_init_irq()
90 clr |= IRQ_NOPROBE; in rpc_init_irq()
100 irq_modify_status(irq, clr, set); in rpc_init_irq()
108 irq_modify_status(irq, clr, set); in rpc_init_irq()
116 irq_modify_status(irq, clr, set); in rpc_init_irq()
123 irq_modify_status(irq, clr, set); in rpc_init_irq()
/Linux-v5.15/arch/m68k/math-emu/
Dfp_util.S70 2: clr.l %d0
99 clr.l %d1 | sign defaults to zero
109 clr.l (%a0)
116 clr.l (%a0)+
117 clr.l (%a0)+
118 clr.l (%a0)
142 clr.l (%a0) | low lword = 0
236 clr.b (%a0)
274 clr.l %d0
279 clr.w -(%a0)
[all …]
/Linux-v5.15/include/trace/events/
Dthp.h49 TP_PROTO(unsigned long addr, unsigned long pte, unsigned long clr, unsigned long set),
50 TP_ARGS(addr, pte, clr, set),
54 __field(unsigned long, clr)
61 __entry->clr = clr;
66 …page update at addr 0x%lx and pte = 0x%lx clr = 0x%lx, set = 0x%lx", __entry->addr, __entry->pte, …
/Linux-v5.15/drivers/video/fbdev/
Datafb_utils.h85 " lsr.l #1,%1 ; jcc 1f ; clr.b (%0)+\n" in fb_memclear()
86 "1: lsr.l #1,%1 ; jcc 1f ; clr.w (%0)+\n" in fb_memclear()
87 "1: lsr.l #1,%1 ; jcc 1f ; clr.l (%0)+\n" in fb_memclear()
88 "1: lsr.l #1,%1 ; jcc 1f ; clr.l (%0)+ ; clr.l (%0)+\n" in fb_memclear()
96 " lsr.l #1,%2 ; jcc 1f ; clr.b (%0)+ ; subq.w #1,%1\n" in fb_memclear()
98 " clr.w (%0)+ ; subq.w #2,%1 ; jra 2f\n" in fb_memclear()
100 " clr.w (%0)+ ; subq.w #2,%1\n" in fb_memclear()
102 " lsr.l #1,%1 ; jcc 3f ; clr.l (%0)+\n" in fb_memclear()
103 "3: lsr.l #1,%1 ; jcc 4f ; clr.l (%0)+ ; clr.l (%0)+\n" in fb_memclear()
105 "5: clr.l (%0)+; clr.l (%0)+ ; clr.l (%0)+ ; clr.l (%0)+\n" in fb_memclear()
[all …]
/Linux-v5.15/arch/m68k/ifpsp060/src/
Ditest.S81 clr.l TESTCTR(%a6)
91 clr.l TESTCTR(%a6)
101 clr.l TESTCTR(%a6)
111 clr.l TESTCTR(%a6)
121 clr.l TESTCTR(%a6)
132 clr.l TESTCTR(%a6)
142 clr.l TESTCTR(%a6)
169 clr.l %d1
181 clr.l IREGS+0x8(%a6)
182 clr.l IREGS+0xc(%a6)
[all …]
/Linux-v5.15/arch/sparc/lib/
Dffs.S14 clr %o0
21 clr %o1 /* 2 */
25 1: clr %o2
31 clr %o3
34 clr %o4
40 clr %o5
/Linux-v5.15/Documentation/admin-guide/
Dmono.rst5 (in the form of .exe files) without the need to use the mono CLR
11 1) You MUST FIRST install the Mono CLR support, either by downloading
21 Once the Mono CLR support has been installed, just check that
50 # Register support for .NET CLR binaries
53 # the Mono CLR runtime (usually /usr/local/bin/mono
55 echo ':CLR:M::MZ::/usr/bin/mono:' > /proc/sys/fs/binfmt_misc/register
/Linux-v5.15/arch/m68k/ifpsp060/
Dos.S94 clr.l %d1 | return success
101 clr.l %d1 | return success
127 clr.l %d1 | return success
134 clr.l %d1 | return success
151 clr.l %d0 | clear whole longword
152 clr.l %d1 | assume success
187 clr.l %d1 | assume success
188 clr.l %d0 | clear whole longword
223 clr.l %d1 | assume success
245 clr.l %d1 | assume success
[all …]
/Linux-v5.15/drivers/staging/media/omap4iss/
Diss.h187 * @clr: bit mask to be cleared
191 u32 offset, u32 clr) in iss_reg_clr() argument
195 iss_reg_write(iss, res, offset, v & ~clr); in iss_reg_clr()
219 * @clr: bit mask to be cleared
222 * Clear the clr mask first and then set the set mask.
226 u32 offset, u32 clr, u32 set) in iss_reg_update() argument
230 iss_reg_write(iss, res, offset, (v & ~clr) | set); in iss_reg_update()
/Linux-v5.15/drivers/clocksource/
Dtimer-armada-370-xp.c91 static void local_timer_ctrl_clrset(u32 clr, u32 set) in local_timer_ctrl_clrset() argument
93 writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set, in local_timer_ctrl_clrset()
176 u32 clr = 0, set = 0; in armada_370_xp_timer_starting_cpu() local
181 clr = TIMER0_25MHZ; in armada_370_xp_timer_starting_cpu()
182 local_timer_ctrl_clrset(clr, set); in armada_370_xp_timer_starting_cpu()
245 u32 clr = 0, set = 0; in armada_370_xp_timer_common_init() local
264 clr = TIMER0_25MHZ; in armada_370_xp_timer_common_init()
267 atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set); in armada_370_xp_timer_common_init()
268 local_timer_ctrl_clrset(clr, set); in armada_370_xp_timer_common_init()
/Linux-v5.15/arch/powerpc/include/asm/
Ddcr-native.h112 unsigned clr, unsigned set) in __dcri_clrset() argument
120 val = (mfdcrx(base_data) & ~clr) | set; in __dcri_clrset()
124 val = (__mfdcr(base_data) & ~clr) | set; in __dcri_clrset()
138 #define dcri_clrset(base, reg, clr, set) __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR, \ argument
140 reg, clr, set)
/Linux-v5.15/drivers/pinctrl/
Dpinctrl-microchip-sgpio.c166 u32 clr, set; in sgpio_configure_bitstream() local
170 clr = SGPIO_LUTON_PORT_WIDTH; in sgpio_configure_bitstream()
175 clr = SGPIO_OCELOT_PORT_WIDTH; in sgpio_configure_bitstream()
180 clr = SGPIO_SPARX5_PORT_WIDTH; in sgpio_configure_bitstream()
187 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set); in sgpio_configure_bitstream()
192 u32 clr, set; in sgpio_configure_clock() local
196 clr = SGPIO_LUTON_CLK_FREQ; in sgpio_configure_clock()
200 clr = SGPIO_OCELOT_CLK_FREQ; in sgpio_configure_clock()
204 clr = SGPIO_SPARX5_CLK_FREQ; in sgpio_configure_clock()
210 sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set); in sgpio_configure_clock()
[all …]
/Linux-v5.15/kernel/irq/
Ddevres.c236 unsigned int clr; member
244 irq_remove_generic_chip(this->gc, this->msk, this->clr, this->set); in devm_irq_remove_generic_chip()
255 * @clr: IRQ_* bits to clear
264 unsigned int clr, unsigned int set) in devm_irq_setup_generic_chip() argument
273 irq_setup_generic_chip(gc, msk, flags, clr, set); in devm_irq_setup_generic_chip()
277 dr->clr = clr; in devm_irq_setup_generic_chip()
Dgeneric-chip.c179 * irq_gc_set_wake - Set/clr wake bit for an interrupt
278 * @clr: IRQ_* bits to clear in the mapping function
285 unsigned int clr, unsigned int set, in __irq_alloc_domain_generic_chips() argument
315 dgc->irq_flags_to_clear = clr; in __irq_alloc_domain_generic_chips()
463 * @clr: IRQ_* bits to clear
471 enum irq_gc_flags flags, unsigned int clr, in irq_setup_generic_chip() argument
502 irq_modify_status(i, clr, set); in irq_setup_generic_chip()
536 * @clr: IRQ_* bits to clear
542 unsigned int clr, unsigned int set) in irq_remove_generic_chip() argument
558 irq_modify_status(i, clr, set); in irq_remove_generic_chip()
/Linux-v5.15/drivers/net/wireless/ath/ath9k/
Dar9003_wow.c127 u32 set, clr; in ath9k_hw_wow_apply_pattern() local
160 clr = AR_WOW_LENGTH1_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
161 REG_RMW(ah, AR_WOW_LENGTH1, set, clr); in ath9k_hw_wow_apply_pattern()
165 clr = AR_WOW_LENGTH2_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
166 REG_RMW(ah, AR_WOW_LENGTH2, set, clr); in ath9k_hw_wow_apply_pattern()
170 clr = AR_WOW_LENGTH3_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
171 REG_RMW(ah, AR_WOW_LENGTH3, set, clr); in ath9k_hw_wow_apply_pattern()
175 clr = AR_WOW_LENGTH4_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
176 REG_RMW(ah, AR_WOW_LENGTH4, set, clr); in ath9k_hw_wow_apply_pattern()
/Linux-v5.15/drivers/net/ethernet/intel/e1000/
De1000_hw.h776 * R/clr - register is read only and is cleared when read
802 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
917 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
918 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
919 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
920 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
921 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
922 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
923 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
924 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
[all …]
/Linux-v5.15/drivers/gpu/drm/nouveau/dispnv50/
Dhead.c43 union nv50_head_atom_mask clr = { in nv50_head_flush_clr() local
44 .mask = asyh->clr.mask & ~(flush ? 0 : asyh->set.mask), in nv50_head_flush_clr()
46 if (clr.crc) nv50_crc_atomic_clr(head); in nv50_head_flush_clr()
47 if (clr.olut) head->func->olut_clr(head); in nv50_head_flush_clr()
48 if (clr.core) head->func->core_clr(head); in nv50_head_flush_clr()
49 if (clr.curs) head->func->curs_clr(head); in nv50_head_flush_clr()
400 asyh->clr.core = true; in nv50_head_atomic_check()
408 asyh->clr.curs = true; in nv50_head_atomic_check()
416 asyh->clr.olut = true; in nv50_head_atomic_check()
419 asyh->clr.olut = armh->olut.visible; in nv50_head_atomic_check()
[all …]
Dwndw.c128 union nv50_wndw_atom_mask clr = { in nv50_wndw_flush_clr() local
129 .mask = asyw->clr.mask & ~(flush ? 0 : asyw->set.mask), in nv50_wndw_flush_clr()
131 if (clr.sema ) wndw->func-> sema_clr(wndw); in nv50_wndw_flush_clr()
132 if (clr.ntfy ) wndw->func-> ntfy_clr(wndw); in nv50_wndw_flush_clr()
133 if (clr.xlut ) wndw->func-> xlut_clr(wndw); in nv50_wndw_flush_clr()
134 if (clr.csc ) wndw->func-> csc_clr(wndw); in nv50_wndw_flush_clr()
135 if (clr.image) wndw->func->image_clr(wndw); in nv50_wndw_flush_clr()
414 asyw->clr.xlut = armw->xlut.handle != 0; in nv50_wndw_atomic_check_lut()
429 asyw->clr.csc = armw->csc.valid; in nv50_wndw_atomic_check_lut()
505 asyw->clr.ntfy = armw->ntfy.handle != 0; in nv50_wndw_atomic_check()
[all …]
/Linux-v5.15/drivers/gpio/
Dgpio-mmio.c471 * - set/clear pair (named "set" and "clr").
476 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
491 void __iomem *clr, in bgpio_setup_io() argument
499 if (set && clr) { in bgpio_setup_io()
501 gc->reg_clr = clr; in bgpio_setup_io()
504 } else if (set && !clr) { in bgpio_setup_io()
583 * @clr: MMIO address for the register to CLEAR the value of the GPIO lines, it is
601 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, in bgpio_init() argument
621 ret = bgpio_setup_io(gc, dat, set, clr, flags); in bgpio_init()
730 void __iomem *clr; in bgpio_pdev_probe() local
[all …]
/Linux-v5.15/arch/powerpc/include/asm/nohash/32/
Dpgtable.h246 unsigned long clr, unsigned long set, int huge) in pte_update() argument
250 pte_basic_t new = (old & ~(pte_basic_t)clr) | set; in pte_update()
275 unsigned long clr, unsigned long set, int huge) in pte_update() argument
278 pte_basic_t new = (old & ~(pte_basic_t)clr) | set; in pte_update()
312 unsigned long clr = ~pte_val(pte_wrprotect(__pte(~0))); in ptep_set_wrprotect() local
315 pte_update(mm, addr, ptep, clr, set, 0); in ptep_set_wrprotect()
326 unsigned long clr = ~pte_val(entry) & ~pte_val(pte_clr); in __ptep_set_access_flags() local
329 pte_update(vma->vm_mm, address, ptep, clr, set, huge); in __ptep_set_access_flags()
/Linux-v5.15/drivers/clk/imx/
Dclk-pfd.c21 * register has SET, CLR and TOG registers at offset 0x4 0x8 and 0xc.
32 #define CLR 0x8 macro
39 writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR); in clk_pfd_enable()
99 writel_relaxed(0x3f << (pfd->idx * 8), pfd->reg + CLR); in clk_pfd_set_rate()
/Linux-v5.15/arch/sparc/include/asm/
Dttable.h18 clr %o0; clr %o1; clr %o2; clr %o3; \
19 clr %o4; clr %o5; clr %o6; clr %o7; \
20 clr %l0; clr %l1; clr %l2; clr %l3; \
21 clr %l4; clr %l5; clr %l6; clr %l7; \

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