Lines Matching full:clr
166 u32 clr, set; in sgpio_configure_bitstream() local
170 clr = SGPIO_LUTON_PORT_WIDTH; in sgpio_configure_bitstream()
175 clr = SGPIO_OCELOT_PORT_WIDTH; in sgpio_configure_bitstream()
180 clr = SGPIO_SPARX5_PORT_WIDTH; in sgpio_configure_bitstream()
187 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set); in sgpio_configure_bitstream()
192 u32 clr, set; in sgpio_configure_clock() local
196 clr = SGPIO_LUTON_CLK_FREQ; in sgpio_configure_clock()
200 clr = SGPIO_OCELOT_CLK_FREQ; in sgpio_configure_clock()
204 clr = SGPIO_SPARX5_CLK_FREQ; in sgpio_configure_clock()
210 sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set); in sgpio_configure_clock()
218 u32 clr, set; in sgpio_output_set() local
222 clr = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, BIT(bit)); in sgpio_output_set()
226 clr = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, BIT(bit)); in sgpio_output_set()
230 clr = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, BIT(bit)); in sgpio_output_set()
236 sgpio_clrsetbits(priv, REG_PORT_CONFIG, addr->port, clr, set); in sgpio_output_set()