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Searched full:clk_top_cci400_sel (Results 1 – 8 of 8) sorted by relevance

/Linux-v6.1/Documentation/devicetree/bindings/media/
Dmediatek,vcodec-decoder.yaml144 <&topckgen CLK_TOP_CCI400_SEL>,
159 <&topckgen CLK_TOP_CCI400_SEL>,
/Linux-v6.1/include/dt-bindings/clock/
Dmediatek,mt6795-clk.h115 #define CLK_TOP_CCI400_SEL 104 macro
Dmt8173-clk.h118 #define CLK_TOP_CCI400_SEL 108 macro
Dmt2712-clk.h155 #define CLK_TOP_CCI400_SEL 124 macro
/Linux-v6.1/drivers/clk/mediatek/
Dclk-mt8173.c579 MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16, 3, 23),
852 clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_CCI400_SEL]->clk); in mtk_clk_enable_critical()
Dclk-mt6795-topckgen.c492 TOP_MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents,
Dclk-mt2712.c795 MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel",
/Linux-v6.1/arch/arm64/boot/dts/mediatek/
Dmt8173.dtsi1399 <&topckgen CLK_TOP_CCI400_SEL>,
1414 <&topckgen CLK_TOP_CCI400_SEL>,